From patchwork Thu Feb 16 22:01:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sinan Kaya X-Patchwork-Id: 9578455 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E4D6E60209 for ; Thu, 16 Feb 2017 22:01:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D27902861C for ; Thu, 16 Feb 2017 22:01:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C729628674; Thu, 16 Feb 2017 22:01:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 367522861C for ; Thu, 16 Feb 2017 22:01:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933446AbdBPWBx (ORCPT ); Thu, 16 Feb 2017 17:01:53 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:59726 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933157AbdBPWBw (ORCPT ); Thu, 16 Feb 2017 17:01:52 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 6665860CE0; Thu, 16 Feb 2017 22:01:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1487282511; bh=vJJ6NQCN+/JTDnDRaGqYQuuP9vnvb0+zSwop+IK+6EA=; h=From:To:Cc:Subject:Date:From; b=BQP/pU0k4Yv5wOuG8wd4vTgB4Sl0UiXaWwzWymlqQdcuviuqNRZ/w2dFfx0SK3ywN WYmSZs68S6N/B2PemCiMuXYuHEAep1MuxO26nUvz6WoTXqpGBhn2E24bLm4tXnzWLp Dm06NE0nsvlm6qNYTjWqvnXaR5K1iWnvrT7Jxy9o= Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 0CBDD60B00; Thu, 16 Feb 2017 22:01:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1487282510; bh=vJJ6NQCN+/JTDnDRaGqYQuuP9vnvb0+zSwop+IK+6EA=; h=From:To:Cc:Subject:Date:From; b=a0ZDcJH7mX2dNd5xZaVGATAnkf3yL1uQ1DN3qJaVSLRplgO+sR22e8L4sTvN1Meck uZc9YN3LnOx4YBNDTPXd1cnBWo80pCIxJJNXKnRbwswgeIs5jglvbuGeFZACE6bpzu HkFzu7/jbPCXpqH7fpckqG0Il1enyLnxjQ4Y3k8k= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 0CBDD60B00 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: linux-pci@vger.kernel.org, timur@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , linux-kernel@vger.kernel.org (open list) Subject: [PATCH V2] PCI: add QCOM root port quirks for ACS Date: Thu, 16 Feb 2017 17:01:45 -0500 Message-Id: <1487282505-26634-1-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 1.9.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP PCI Express defines an optional featured called Access Control Services described in 6.12. Access Control Services (ACS) section of the PCIe 3.1 Specification. Linux kernel uses ACS to validate/prohibit data transfers among PCIe functions. This becomes especially useful when running guest machines with PCI device passthrough. It provides security guarantee that only OS allowed PCIe devices can talk to each other. QCOM root ports do provide ACS-like features to disable peer transactions and validate bus numbers in requests, but do not provide an actual PCIe ACS capability. To be specific: * Hardware supports source validation but it will report the issue as Completer Abort instead of ACS Violation. * Hardware doesn't support peer-to-peer and each root port is a root complex with unique segment numbers. * It is not possible for one root port to pass traffic to the other root port. All PCIe transactions are terminated inside the root port. Adding an ACS quirk for the QDF2400 and QDF2432 products. Signed-off-by: Sinan Kaya Reviewed-by: Alex Williamson --- drivers/pci/quirks.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 1800bef..2df06cb 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4136,6 +4136,27 @@ static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) } /* + * These QCOM root ports do provide ACS-like features to disable peer + * transactions and validate bus numbers in requests, but do not provide an + * actual PCIe ACS capability. + * Hardware supports source validation but it will report the issue as + * Completer Abort instead of ACS Violation. + * Hardware doesn't support peer-to-peer and each root port is a root complex + * with unique segment numbers. + * It is not possible for one root port to pass traffic to the other root + * port. All PCIe transactions are terminated inside the root port. + */ +static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) +{ + u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV); + int ret = acs_flags & ~flags ? 0 : 1; + + dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret); + + return ret; +} + +/* * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and @@ -4271,6 +4292,9 @@ static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) /* I219 */ { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, + /* QCOM QDF2xxx root ports */ + { 0x17CB, 0x400, pci_quirk_qcom_rp_acs }, + { 0x17CB, 0x401, pci_quirk_qcom_rp_acs }, /* Intel PCH root ports */ { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },