From patchwork Mon Mar 6 11:40:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christian_K=C3=B6nig?= X-Patchwork-Id: 9605893 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4154B602B4 for ; Mon, 6 Mar 2017 11:50:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2067B28305 for ; Mon, 6 Mar 2017 11:50:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 14E4928249; Mon, 6 Mar 2017 11:50:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A04D328305 for ; Mon, 6 Mar 2017 11:50:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753621AbdCFLuA (ORCPT ); Mon, 6 Mar 2017 06:50:00 -0500 Received: from pegasos-out.vodafone.de ([80.84.1.38]:48351 "EHLO pegasos-out.vodafone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753593AbdCFLt5 (ORCPT ); Mon, 6 Mar 2017 06:49:57 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by pegasos-out.vodafone.de (Rohrpostix1 Daemon) with ESMTP id 59DA1261EE3; Mon, 6 Mar 2017 12:40:33 +0100 (CET) X-Virus-Scanned: amavisd-new at vodafone.de Authentication-Results: rohrpostix1.prod.vfnet.de (amavisd-new); dkim=pass header.i=@vodafone.de Received: from pegasos-out.vodafone.de ([127.0.0.1]) by localhost (rohrpostix1.prod.vfnet.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qTFEt8C0aeyf; Mon, 6 Mar 2017 12:40:30 +0100 (CET) Received: from smtp-01.vodafone.de (xsmail-dmz5.prod.vfnet.de [10.215.254.36]) by pegasos-out.vodafone.de (Rohrpostix1 Daemon) with ESMTP id 802EA261E49; Mon, 6 Mar 2017 12:40:30 +0100 (CET) X-DKIM: OpenDKIM Filter v2.6.8 pegasos-out.vodafone.de 802EA261E49 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vodafone.de; s=mail; t=1488800430; bh=ZPlmyQ40g4IKthn+VKe5FJyefuFUK0YuWo9ednGEPLU=; h=From:To:Subject:Date; b=WcQideoUfLrSyiziAptMQZwDEVKU/+SNmIz0nG0aw0NMVfTnCFNV3514aH1y6sLmB zNMeiUOdX7Lsr2IWu0pU/3Q62GTat1uNsnU2SWktbvs217t5d6nTUsraE77vY9Q3np Ynld0DF0hw+rHFtdgd8nOK2/1+ttKSKd032YtH+A= X-DKIM: OpenDKIM Filter v2.0.2 smtp-01.vodafone.de E72B1E5391 X-Virus-Scanned: amavisd-new at vodafone.de Received: from smtp-01.vodafone.de ([127.0.0.1]) by localhost (xsmail-dmz5.prod.vfnet.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id auxKut7RKenW; Mon, 6 Mar 2017 12:40:29 +0100 (CET) From: =?UTF-8?q?Christian=20K=C3=B6nig?= To: linux-pci@vger.kernel.org, dri-devel@lists.freedesktop.org, platform-driver-x86@vger.kernel.org, amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] PCI: add resizeable BAR infrastructure v2 Date: Mon, 6 Mar 2017 12:40:24 +0100 Message-Id: <1488800428-2854-1-git-send-email-deathsimple@vodafone.de> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Christian König Just the defines and helper functions to read the possible sizes of a BAR and update it's size. See https://pcisig.com/sites/default/files/specification_documents/ECN_Resizable-BAR_24Apr2008.pdf. v2: provide read helper as well Signed-off-by: Christian König --- drivers/pci/pci.c | 115 ++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 3 ++ include/uapi/linux/pci_regs.h | 7 +++ 3 files changed, 125 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index ba34907..9658aa7 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2944,6 +2944,121 @@ bool pci_acs_path_enabled(struct pci_dev *start, } /** + * pci_rbar_get_sizes - get possible sizes for BAR + * @dev: PCI device + * @bar: BAR to query + * + * Get the possible sizes of a resizeable BAR as bitmask defined in the spec + * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizeable. + */ +u32 pci_rbar_get_sizes(struct pci_dev *pdev, int bar) +{ + int pos, nbars; + u32 ctrl, cap; + int i; + + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); + if (!pos) + return 0x0; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> PCI_REBAR_CTRL_NBAR_SHIFT; + + for (i = 0; i < nbars; ++i, pos += 8) { + int bar_idx; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + bar_idx = (ctrl & PCI_REBAR_CTRL_BAR_IDX_MASK) >> + PCI_REBAR_CTRL_BAR_IDX_SHIFT; + if (bar_idx != bar) + continue; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); + return (cap & PCI_REBAR_CTRL_SIZES_MASK) >> + PCI_REBAR_CTRL_SIZES_SHIFT; + } + + return 0x0; +} + +/** + * pci_rbar_get_size - get the current size of a BAR + * @dev: PCI device + * @bar: BAR to set size to + * + * Read the size of a BAR from the resizeable BAR config. + * Returns size if found or negativ error code. + */ +int pci_rbar_get_size(struct pci_dev *pdev, int bar) +{ + int pos, nbars; + u32 ctrl; + int i; + + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); + if (!pos) + return -ENOTSUPP; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> PCI_REBAR_CTRL_NBAR_SHIFT; + + for (i = 0; i < nbars; ++i, pos += 8) { + int bar_idx; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + bar_idx = (ctrl & PCI_REBAR_CTRL_BAR_IDX_MASK) >> + PCI_REBAR_CTRL_BAR_IDX_SHIFT; + if (bar_idx != bar) + continue; + + return (ctrl & PCI_REBAR_CTRL_BAR_SIZE_MASK) >> + PCI_REBAR_CTRL_BAR_SIZE_SHIFT; + } + + return -ENOENT; +} + +/** + * pci_rbar_set_size - set a new size for a BAR + * @dev: PCI device + * @bar: BAR to set size to + * @size: new size as defined in the spec. + * + * Set the new size of a BAR as defined in the spec (0=1MB, 19=512GB). + * Returns true if resizing was successful, false otherwise. + */ +bool pci_rbar_set_size(struct pci_dev *pdev, int bar, int size) +{ + int pos, nbars; + u32 ctrl; + int i; + + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); + if (!pos) + return false; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> PCI_REBAR_CTRL_NBAR_SHIFT; + + for (i = 0; i < nbars; ++i, pos += 8) { + int bar_idx; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + bar_idx = (ctrl & PCI_REBAR_CTRL_BAR_IDX_MASK) >> + PCI_REBAR_CTRL_BAR_IDX_SHIFT; + if (bar_idx != bar) + continue; + + ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE_MASK; + ctrl |= size << PCI_REBAR_CTRL_BAR_SIZE_SHIFT; + pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); + return true; + } + + return false; +} + +/** * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge * @dev: the PCI device * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) diff --git a/include/linux/pci.h b/include/linux/pci.h index a38772a..9f26ca4 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1946,6 +1946,9 @@ void pci_request_acs(void); bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); bool pci_acs_path_enabled(struct pci_dev *start, struct pci_dev *end, u16 acs_flags); +u32 pci_rbar_get_sizes(struct pci_dev *pdev, int bar); +int pci_rbar_get_size(struct pci_dev *pdev, int bar); +bool pci_rbar_set_size(struct pci_dev *pdev, int bar, int size); #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index e5a2e68..6de29d6 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -932,9 +932,16 @@ #define PCI_SATA_SIZEOF_LONG 16 /* Resizable BARs */ +#define PCI_REBAR_CAP 4 /* capability register */ +#define PCI_REBAR_CTRL_SIZES_MASK (0xFFFFF << 4) /* mask for sizes */ +#define PCI_REBAR_CTRL_SIZES_SHIFT 4 /* shift for sizes */ #define PCI_REBAR_CTRL 8 /* control register */ +#define PCI_REBAR_CTRL_BAR_IDX_MASK (7 << 0) /* mask for bar index */ +#define PCI_REBAR_CTRL_BAR_IDX_SHIFT 0 /* shift for bar index */ #define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */ #define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */ +#define PCI_REBAR_CTRL_BAR_SIZE_MASK (0x1F << 8) /* mask for bar size */ +#define PCI_REBAR_CTRL_BAR_SIZE_SHIFT 8 /* shift for bar size */ /* Dynamic Power Allocation */ #define PCI_DPA_CAP 4 /* capability register */