From patchwork Wed Mar 8 10:47:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 9610803 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BC3E66016C for ; Wed, 8 Mar 2017 10:57:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B78E91FFB7 for ; Wed, 8 Mar 2017 10:57:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AC3EA2846A; Wed, 8 Mar 2017 10:57:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3568B2846E for ; Wed, 8 Mar 2017 10:57:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752738AbdCHK5L (ORCPT ); Wed, 8 Mar 2017 05:57:11 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:26791 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752110AbdCHKzh (ORCPT ); Wed, 8 Mar 2017 05:55:37 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v28Am7oC001775; Wed, 8 Mar 2017 04:48:07 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1488970087; bh=UVlaOSv9tqVdYi5RNfERXy64rAHbzGSj1uo0KbJIMU8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yGpjXfJMpMe2MZKX4K4cL5L45s2ovwxGK4yktOtEhUyagnPIBuxD5iibrcBFbnJl9 /CBmbBa7CzNvv7i2lPGFaUrWKggtA8jcf5uVBzg2OmLboe+RyrhIKtpeyisaaCttUs j9h6++s7YyLloLErEA9h6JbkTlBp7DDQoNphK0dQ= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v28Am6Nx020060; Wed, 8 Mar 2017 04:48:06 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Wed, 8 Mar 2017 04:48:06 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v28AlJ2D000570; Wed, 8 Mar 2017 04:48:03 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , Kishon Vijay Abraham I Subject: [PATCH v3 6/7] PCI: dwc: designware: Move _unroll configurations to a separate function Date: Wed, 8 Mar 2017 16:17:16 +0530 Message-ID: <1488970037-17740-7-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1488970037-17740-1-git-send-email-kishon@ti.com> References: <1488970037-17740-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP No functional change. Rename dw_pcie_writel_unroll/dw_pcie_readl_unroll to dw_pcie_writel_ob_unroll/dw_pcie_readl_ob_unroll respectively as these functions are used to perform only outbound configurations. Also move these _unroll configurations to a separate function. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pcie-designware.c | 112 ++++++++++++++++++++++--------------- 1 file changed, 67 insertions(+), 45 deletions(-) diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index 557ee53..6657a84 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -92,22 +92,64 @@ void dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, dev_err(pci->dev, "write DBI address failed\n"); } -static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base, - u32 index, u32 reg) +static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, void __iomem *base, + u32 index, u32 reg) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); return dw_pcie_read_dbi(pci, base, offset + reg, 0x4); } -static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base, - u32 index, u32 reg, u32 val) +static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, void __iomem *base, + u32 index, u32 reg, u32 val) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val); } +void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index, int type, + u64 cpu_addr, u64 pci_addr, u32 size) +{ + u32 retries, val; + void __iomem *base = pci->dbi_base; + + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_LOWER_BASE, + lower_32_bits(cpu_addr)); + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_UPPER_BASE, + upper_32_bits(cpu_addr)); + dw_pcie_writel_ob_unroll(pci, base, index, PCIE_ATU_UNR_LIMIT, + lower_32_bits(cpu_addr + size - 1)); + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_LOWER_TARGET, + lower_32_bits(pci_addr)); + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_UPPER_TARGET, + upper_32_bits(pci_addr)); + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_REGION_CTRL1, + type); + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_REGION_CTRL2, + PCIE_ATU_ENABLE); + + /* + * Make sure ATU enable takes effect before any subsequent config + * and I/O accesses. + */ + for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { + val = dw_pcie_readl_ob_unroll(pci, base, index, + PCIE_ATU_UNR_REGION_CTRL2); + if (val & PCIE_ATU_ENABLE) + return; + + usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); + } + dev_err(pci->dev, "outbound iATU is not being enabled\n"); +} + void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, u64 cpu_addr, u64 pci_addr, u32 size) { @@ -118,59 +160,39 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr); if (pci->iatu_unroll_enabled) { - dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LOWER_BASE, - lower_32_bits(cpu_addr)); - dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_UPPER_BASE, - upper_32_bits(cpu_addr)); - dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LIMIT, - lower_32_bits(cpu_addr + size - 1)); - dw_pcie_writel_unroll(pci, base, index, - PCIE_ATU_UNR_LOWER_TARGET, - lower_32_bits(pci_addr)); - dw_pcie_writel_unroll(pci, base, index, - PCIE_ATU_UNR_UPPER_TARGET, - upper_32_bits(pci_addr)); - dw_pcie_writel_unroll(pci, base, index, - PCIE_ATU_UNR_REGION_CTRL1, - type); - dw_pcie_writel_unroll(pci, base, index, - PCIE_ATU_UNR_REGION_CTRL2, - PCIE_ATU_ENABLE); - } else { - dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4, - PCIE_ATU_REGION_OUTBOUND | index); - dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_BASE, 0x4, - lower_32_bits(cpu_addr)); - dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_BASE, 0x4, - upper_32_bits(cpu_addr)); - dw_pcie_write_dbi(pci, base, PCIE_ATU_LIMIT, 0x4, - lower_32_bits(cpu_addr + size - 1)); - dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4, - lower_32_bits(pci_addr)); - dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4, - upper_32_bits(pci_addr)); - dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type); - dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, - PCIE_ATU_ENABLE); + dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr, + pci_addr, size); + return; } + dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4, + PCIE_ATU_REGION_OUTBOUND | index); + dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_BASE, 0x4, + lower_32_bits(cpu_addr)); + dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_BASE, 0x4, + upper_32_bits(cpu_addr)); + dw_pcie_write_dbi(pci, base, PCIE_ATU_LIMIT, 0x4, + lower_32_bits(cpu_addr + size - 1)); + dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4, + lower_32_bits(pci_addr)); + dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4, + upper_32_bits(pci_addr)); + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type); + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, + PCIE_ATU_ENABLE); + /* * Make sure ATU enable takes effect before any subsequent config * and I/O accesses. */ for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { - if (pci->iatu_unroll_enabled) - val = dw_pcie_readl_unroll(pci, base, index, - PCIE_ATU_UNR_REGION_CTRL2); - else - val = dw_pcie_read_dbi(pci, base, PCIE_ATU_CR2, 0x4); - + val = dw_pcie_read_dbi(pci, base, PCIE_ATU_CR2, 0x4); if (val == PCIE_ATU_ENABLE) return; usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); } - dev_err(pci->dev, "iATU is not being enabled\n"); + dev_err(pci->dev, "outbound iATU is not being enabled\n"); } int dw_pcie_wait_for_link(struct dw_pcie *pci)