From patchwork Sat Mar 25 05:31:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oza Pawandeep X-Patchwork-Id: 9644399 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8DCFB6020B for ; Sat, 25 Mar 2017 05:32:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7FE2F205AB for ; Sat, 25 Mar 2017 05:32:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 74BF52621D; Sat, 25 Mar 2017 05:32:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 63E18252D5 for ; Sat, 25 Mar 2017 05:32:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S967008AbdCYFcL (ORCPT ); Sat, 25 Mar 2017 01:32:11 -0400 Received: from mail-wm0-f47.google.com ([74.125.82.47]:35224 "EHLO mail-wm0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966965AbdCYFb7 (ORCPT ); Sat, 25 Mar 2017 01:31:59 -0400 Received: by mail-wm0-f47.google.com with SMTP id u132so26470248wmg.0 for ; Fri, 24 Mar 2017 22:31:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+1XXPr1ai1AFdZaL6cFthOCyQGCD6YnzhI4zFdyahm8=; b=IdtGcp1z2Gjpd3kVGkljtS/V0MwtCREpjCsltXg3IX1UsVVkmHdpCbF9boglDRTetW a5lzq5Ofi2X/OUri7xIf2Lyczcujoc7XAKHY9h4eobkERXrtw/x4RRelZjtA7ilecHAz 3KZpFow3rJrMRjmaRz/LyL4RNYz9ettegiDeY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+1XXPr1ai1AFdZaL6cFthOCyQGCD6YnzhI4zFdyahm8=; b=R45bCkjS+wiQkNSEsO0qkJ8CBExBqSQL0z0/ilNlEV8ueoQG8wlqAn5zrRjAL5tGeE WHoo7RMLK3agorZNq2QksuxRmGesTjMPLW/YLdCwttTAn9pA4gQAPxoc931HYYeadrE6 hUFjMRrMcSf3jHblO7oSyHVBuu4jKzg1mXPm17RZQpt5f4n3bxQwW7SJoB8T0r3Pvfek WXeLfqKf3P4JZ8mjUTwskex3g5AHLEFdSuEz5k8i8BSZR3A4w4CxkO57/5y+y5P5ZhbF b7JWln5gZgQ1+xX4JNYUEg3me1vOMH2sXNQbmot/w5hFwqysE6hHiIeie9QKFEKE/PBR O6cQ== X-Gm-Message-State: AFeK/H23ye6euRMtuE+JRdY41N/f1qe6RnC9OQ1jnFjGLIXwnsEQ6hK/mI4ildAHYHZCkd8u X-Received: by 10.28.135.149 with SMTP id j143mr627352wmd.19.1490419912250; Fri, 24 Mar 2017 22:31:52 -0700 (PDT) Received: from anjanavk-OptiPlex-7010.dhcp.avagotech.net ([192.19.237.250]) by smtp.gmail.com with ESMTPSA id x1sm5479205wrd.63.2017.03.24.22.31.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 Mar 2017 22:31:51 -0700 (PDT) From: Oza Pawandeep To: Joerg Roedel , Robin Murphy Cc: iommu@lists.linux-foundation.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, Oza Pawandeep Subject: [RFC PATCH 2/3] iommu/dma: account pci host bridge dma_mask for IOVA allocation Date: Sat, 25 Mar 2017 11:01:32 +0530 Message-Id: <1490419893-5073-2-git-send-email-oza.oza@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490419893-5073-1-git-send-email-oza.oza@broadcom.com> References: <1490419893-5073-1-git-send-email-oza.oza@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP it is possible that PCI device supports 64-bit DMA addressing, and thus it's driver sets device's dma_mask to DMA_BIT_MASK(64), however PCI host bridge may have limitations on the inbound transaction addressing. As an example, consider NVME SSD device connected to iproc-PCIe controller. Currently, the IOMMU DMA ops only considers PCI device dma_mask when allocating an IOVA. This is particularly problematic on ARM/ARM64 SOCs where the IOMMU (i.e. SMMU) translates IOVA to PA for in-bound transactions only after PCI Host has forwarded these transactions on SOC IO bus. This means on such ARM/ARM64 SOCs the IOVA of in-bound transactions has to honor the addressing restrictions of the PCI Host. this patch is inspired by http://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1306545.html http://www.spinics.net/lists/arm-kernel/msg566947.html but above inspiraiton solves the half of the problem. the rest of the problem is descrbied below, what we face on iproc based SOCs. current pcie frmework and of framework integration assumes dma-ranges in a way where memory-mapped devices define their dma-ranges. dma-ranges: (child-bus-address, parent-bus-address, length). but iproc based SOCs and even Rcar based SOCs has PCI world dma-ranges. dma-ranges = <0x43000000 0x00 0x00 0x00 0x00 0x80 0x00>; of_dma_configure is specifically witten to take care of memory mapped devices. but no implementation exists for pci to take care of pcie based memory ranges. in fact pci world doesnt seem to define standard dma-ranges this patch implements of_pci_get_dma_ranges to cater to pci world dma-ranges. so then the returned size get best possible (largest) dma_mask. for e.g. dma-ranges = <0x43000000 0x00 0x00 0x00 0x00 0x80 0x00>; we should get dev->coherent_dma_mask=0x7fffffffff. Reviewed-by: Anup Patel Reviewed-by: Scott Branden Signed-off-by: Oza Pawandeep diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 8c7c244..20cfff7 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -217,6 +217,9 @@ config NEED_DMA_MAP_STATE config NEED_SG_DMA_LENGTH def_bool y +config ARCH_HAS_DMA_SET_COHERENT_MASK + def_bool y + config SMP def_bool y diff --git a/arch/arm64/include/asm/device.h b/arch/arm64/include/asm/device.h index 73d5bab..64b4dc3 100644 --- a/arch/arm64/include/asm/device.h +++ b/arch/arm64/include/asm/device.h @@ -20,6 +20,7 @@ struct dev_archdata { #ifdef CONFIG_IOMMU_API void *iommu; /* private IOMMU data */ #endif + u64 parent_dma_mask; bool dma_coherent; }; diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index 81cdb2e..5845ecd 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -564,6 +564,7 @@ static void flush_page(struct device *dev, const void *virt, phys_addr_t phys) __dma_flush_area(virt, PAGE_SIZE); } + static void *__iommu_alloc_attrs(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, unsigned long attrs) @@ -795,6 +796,20 @@ static void __iommu_unmap_sg_attrs(struct device *dev, iommu_dma_unmap_sg(dev, sgl, nelems, dir, attrs); } +static int __iommu_set_dma_mask(struct device *dev, u64 mask) +{ + /* device is not DMA capable */ + if (!dev->dma_mask) + return -EIO; + + if (mask > dev->archdata.parent_dma_mask) + mask = dev->archdata.parent_dma_mask; + + *dev->dma_mask = mask; + + return 0; +} + static const struct dma_map_ops iommu_dma_ops = { .alloc = __iommu_alloc_attrs, .free = __iommu_free_attrs, @@ -811,8 +826,21 @@ static void __iommu_unmap_sg_attrs(struct device *dev, .map_resource = iommu_dma_map_resource, .unmap_resource = iommu_dma_unmap_resource, .mapping_error = iommu_dma_mapping_error, + .set_dma_mask = __iommu_set_dma_mask, }; +int dma_set_coherent_mask(struct device *dev, u64 mask) +{ + if (get_dma_ops(dev) == &iommu_dma_ops && + mask > dev->archdata.parent_dma_mask) + mask = dev->archdata.parent_dma_mask; + + dev->coherent_dma_mask = mask; + return 0; +} +EXPORT_SYMBOL(dma_set_coherent_mask); + + /* * TODO: Right now __iommu_setup_dma_ops() gets called too early to do * everything it needs to - the device is only partially created and the @@ -975,6 +1003,8 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, if (!dev->dma_ops) dev->dma_ops = &swiotlb_dma_ops; + dev->archdata.parent_dma_mask = size - 1; + dev->archdata.dma_coherent = coherent; __iommu_setup_dma_ops(dev, dma_base, size, iommu); } diff --git a/drivers/of/device.c b/drivers/of/device.c index d362a98..471dcdf 100644 --- a/drivers/of/device.c +++ b/drivers/of/device.c @@ -139,10 +139,8 @@ void of_dma_configure(struct device *dev, struct device_node *np) * Limit coherent and dma mask based on size and default mask * set by the driver. */ - dev->coherent_dma_mask = min(dev->coherent_dma_mask, - DMA_BIT_MASK(ilog2(dma_addr + size))); - *dev->dma_mask = min((*dev->dma_mask), - DMA_BIT_MASK(ilog2(dma_addr + size))); + dev->coherent_dma_mask = DMA_BIT_MASK(ilog2(dma_addr + size)); + *dev->dma_mask = dev->coherent_dma_mask; coherent = of_dma_is_coherent(np); dev_dbg(dev, "device is%sdma coherent\n",