From patchwork Fri May 5 14:00:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oza Pawandeep X-Patchwork-Id: 9713615 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EB33960362 for ; Fri, 5 May 2017 14:01:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E190B286B8 for ; Fri, 5 May 2017 14:01:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D475F286A0; Fri, 5 May 2017 14:01:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 75454286A0 for ; Fri, 5 May 2017 14:01:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753286AbdEEOA4 (ORCPT ); Fri, 5 May 2017 10:00:56 -0400 Received: from mail-wm0-f42.google.com ([74.125.82.42]:38882 "EHLO mail-wm0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752410AbdEEOAy (ORCPT ); Fri, 5 May 2017 10:00:54 -0400 Received: by mail-wm0-f42.google.com with SMTP id 142so7236034wma.1 for ; Fri, 05 May 2017 07:00:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1RCSD1k10sHTXjN2JnPBku868qtEqKI+6iwQ82iuCuY=; b=V1QWID8nibhQI3VQpkoNx82MnOm44fwjDpIt8xlHGwBERllguoomasFJW2IO/nz+3f Ti27Fp1wy7MjVfIgFOHHPjSl1kfS1bp1fFKAf/AAYoa+VcmQ6qZDwPb1sZt5nGcfe9Og yMKNR9/tRyu6TEkXJWuz1grXjEri/ZrNYwmOc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1RCSD1k10sHTXjN2JnPBku868qtEqKI+6iwQ82iuCuY=; b=DzNEzOZ07d+9ZNCHRC8sE3l71KOPVNuiCN0bN7JUp8el2vBQF07fKUCuUC+b/jWNjf nbJXmwSBUQw138Af/f1M6XALyUkfYYCsOuosCFdP3VDQrWMrkJ8HV1POjGu55RH1mBKm qtIfYU30m9wAeyn/Kwk9zltISRE2a0VsmxnWD6BkrMT3ER2xOls3KfvxaU5IPOQk3iEm JO9wXG3LhPRpAlHxmbVGRsSrAMmaLMAJQBDt8c2bD5eIeufDqdY0mvSckKdNSXmEqRLH tvad8oFg9GnoQuY/LDWaKmGaDtCk9ZhL2lVrm0dP3n3NQ/uXHohULTH28eDB9n3fa21+ ZNKA== X-Gm-Message-State: AODbwcCu4SrYKp9Lm3TVcVpdTvYp8RwiH8dOZOEmnfEcDW/TPSUmoKL9 tWujTpH166/74lSr X-Received: by 10.28.158.212 with SMTP id h203mr5770813wme.139.1493992853381; Fri, 05 May 2017 07:00:53 -0700 (PDT) Received: from anjanavk-OptiPlex-7010.dhcp.avagotech.net ([192.19.237.250]) by smtp.gmail.com with ESMTPSA id 188sm2264174wmf.29.2017.05.05.07.00.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 05 May 2017 07:00:52 -0700 (PDT) From: Oza Pawandeep To: Joerg Roedel , Robin Murphy Cc: iommu@lists.linux-foundation.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, Oza Pawandeep , Oza Pawandeep Subject: [PATCH v5 2/3] iommu/pci: reserve IOVA for PCI masters Date: Fri, 5 May 2017 19:30:26 +0530 Message-Id: <1493992827-1553-3-git-send-email-oza.oza@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1493992827-1553-1-git-send-email-oza.oza@broadcom.com> References: <1493992827-1553-1-git-send-email-oza.oza@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP this patch reserves the IOVA for PCI masters. ARM64 based SOCs may have scattered memory banks. such as iproc based SOC has <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ <0x00000008 0x80000000 0x3 0x80000000>, /* 14G @ 34G */ <0x00000090 0x00000000 0x4 0x00000000>, /* 16G @ 576G */ <0x000000a0 0x00000000 0x4 0x00000000>; /* 16G @ 640G */ but incoming PCI transcation addressing capability is limited by host bridge, for example if max incoming window capability is 512 GB, then 0x00000090 and 0x000000a0 will fall beyond it. to address this problem, iommu has to avoid allocating IOVA which are reserved. which inturn does not allocate IOVA if it falls into hole. Signed-off-by: Oza Pawandeep diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 48d36ce..08764b0 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -171,8 +172,12 @@ static void iova_reserve_pci_windows(struct pci_dev *dev, struct iova_domain *iovad) { struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus); + struct device_node *np = bridge->dev.parent->of_node; struct resource_entry *window; unsigned long lo, hi; + int ret; + dma_addr_t tmp_dma_addr = 0, dma_addr; + LIST_HEAD(res); resource_list_for_each_entry(window, &bridge->windows) { if (resource_type(window->res) != IORESOURCE_MEM && @@ -183,6 +188,36 @@ static void iova_reserve_pci_windows(struct pci_dev *dev, hi = iova_pfn(iovad, window->res->end - window->offset); reserve_iova(iovad, lo, hi); } + + /* PCI inbound memory reservation. */ + ret = of_pci_get_dma_ranges(np, &res); + if (!ret) { + resource_list_for_each_entry(window, &res) { + struct resource *res_dma = window->res; + + dma_addr = res_dma->start - window->offset; + if (tmp_dma_addr > dma_addr) { + pr_warn("PCI: failed to reserve iovas; ranges should be sorted\n"); + return; + } + if (tmp_dma_addr != dma_addr) { + lo = iova_pfn(iovad, tmp_dma_addr); + hi = iova_pfn(iovad, dma_addr - 1); + reserve_iova(iovad, lo, hi); + } + tmp_dma_addr = window->res->end - window->offset; + } + /* + * the last dma-range should honour based on the + * 32/64-bit dma addresses. + */ + if (tmp_dma_addr < DMA_BIT_MASK(sizeof(dma_addr_t) * 8)) { + lo = iova_pfn(iovad, tmp_dma_addr); + hi = iova_pfn(iovad, + DMA_BIT_MASK(sizeof(dma_addr_t) * 8) - 1); + reserve_iova(iovad, lo, hi); + } + } } /**