From patchwork Tue May 16 05:22:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oza Pawandeep X-Patchwork-Id: 9728339 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0A4FE60386 for ; Tue, 16 May 2017 05:23:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F3556286EF for ; Tue, 16 May 2017 05:23:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E7FF7289DC; Tue, 16 May 2017 05:23:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_HI,RCVD_IN_SORBS_SPAM autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8DBF2286EF for ; Tue, 16 May 2017 05:23:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751309AbdEPFWs (ORCPT ); Tue, 16 May 2017 01:22:48 -0400 Received: from mail-wm0-f47.google.com ([74.125.82.47]:36734 "EHLO mail-wm0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751401AbdEPFWp (ORCPT ); Tue, 16 May 2017 01:22:45 -0400 Received: by mail-wm0-f47.google.com with SMTP id u65so107985600wmu.1 for ; Mon, 15 May 2017 22:22:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1RCSD1k10sHTXjN2JnPBku868qtEqKI+6iwQ82iuCuY=; b=Zws5ggZfXW7A+8RIB+2rg+9luPnfLI+ML5lR0LasAL7UC76v5gN977REm5tbtEe26C j7MiRju36VZMhGQjPRW9rR/Vw4m1/N+iUtPjfE1677sGH1SLc5M4qjMfRnuMctp9zVKR QoVYG7FqVxUewB61VTxZfrI311ywX2OesxaSw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1RCSD1k10sHTXjN2JnPBku868qtEqKI+6iwQ82iuCuY=; b=U2HkzVpkbUNXufs7TriFKEO3+qhFuAfSQiKUCCew9Li8ay/Yp0nJW0MYUZdhXATjs2 9ccEQ3PBy8f/xokcqNbOUud6xiQ+kof3HAUERfZTIX4rxoE4usUZEI7Rx22JEN5TjG4x R6xcQBpqJx6ebmnZNtHYGAxOdhC6jUDXFZRr++wLZx4Rl85vHIya3ANSqSEouZXRTQeK wrJ0q7sbdPdgh4iuiPIWLVhxHgAOEPtK8d/brJJYGz27gVltbWI6Zoc/TDBRfhkgI3w0 Ygr7mc2J+logAhQHQ8bOt2v7TL5724Q0CvWL6R6g76iigtY75WlqsC50fdvKAoUE2Dig 5Z+w== X-Gm-Message-State: AODbwcBmuTzkFIDN8WVNn7ZXwZAHN75y1TMB0IBcYOjEh4IprSwlgvQO P/fj1q5QeavoROf7 X-Received: by 10.28.84.81 with SMTP id p17mr5446148wmi.53.1494912154349; Mon, 15 May 2017 22:22:34 -0700 (PDT) Received: from anjanavk-OptiPlex-7010.dhcp.avagotech.net ([192.19.237.250]) by smtp.gmail.com with ESMTPSA id m201sm1053073wmd.15.2017.05.15.22.22.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 15 May 2017 22:22:33 -0700 (PDT) From: Oza Pawandeep To: Joerg Roedel , Robin Murphy Cc: iommu@lists.linux-foundation.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, Oza Pawandeep , Oza Pawandeep Subject: [PATCH v6 2/3] iommu/pci: reserve IOVA for PCI masters Date: Tue, 16 May 2017 10:52:06 +0530 Message-Id: <1494912127-12890-3-git-send-email-oza.oza@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1494912127-12890-1-git-send-email-oza.oza@broadcom.com> References: <1494912127-12890-1-git-send-email-oza.oza@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP this patch reserves the IOVA for PCI masters. ARM64 based SOCs may have scattered memory banks. such as iproc based SOC has <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ <0x00000008 0x80000000 0x3 0x80000000>, /* 14G @ 34G */ <0x00000090 0x00000000 0x4 0x00000000>, /* 16G @ 576G */ <0x000000a0 0x00000000 0x4 0x00000000>; /* 16G @ 640G */ but incoming PCI transcation addressing capability is limited by host bridge, for example if max incoming window capability is 512 GB, then 0x00000090 and 0x000000a0 will fall beyond it. to address this problem, iommu has to avoid allocating IOVA which are reserved. which inturn does not allocate IOVA if it falls into hole. Signed-off-by: Oza Pawandeep diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 48d36ce..08764b0 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -171,8 +172,12 @@ static void iova_reserve_pci_windows(struct pci_dev *dev, struct iova_domain *iovad) { struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus); + struct device_node *np = bridge->dev.parent->of_node; struct resource_entry *window; unsigned long lo, hi; + int ret; + dma_addr_t tmp_dma_addr = 0, dma_addr; + LIST_HEAD(res); resource_list_for_each_entry(window, &bridge->windows) { if (resource_type(window->res) != IORESOURCE_MEM && @@ -183,6 +188,36 @@ static void iova_reserve_pci_windows(struct pci_dev *dev, hi = iova_pfn(iovad, window->res->end - window->offset); reserve_iova(iovad, lo, hi); } + + /* PCI inbound memory reservation. */ + ret = of_pci_get_dma_ranges(np, &res); + if (!ret) { + resource_list_for_each_entry(window, &res) { + struct resource *res_dma = window->res; + + dma_addr = res_dma->start - window->offset; + if (tmp_dma_addr > dma_addr) { + pr_warn("PCI: failed to reserve iovas; ranges should be sorted\n"); + return; + } + if (tmp_dma_addr != dma_addr) { + lo = iova_pfn(iovad, tmp_dma_addr); + hi = iova_pfn(iovad, dma_addr - 1); + reserve_iova(iovad, lo, hi); + } + tmp_dma_addr = window->res->end - window->offset; + } + /* + * the last dma-range should honour based on the + * 32/64-bit dma addresses. + */ + if (tmp_dma_addr < DMA_BIT_MASK(sizeof(dma_addr_t) * 8)) { + lo = iova_pfn(iovad, tmp_dma_addr); + hi = iova_pfn(iovad, + DMA_BIT_MASK(sizeof(dma_addr_t) * 8) - 1); + reserve_iova(iovad, lo, hi); + } + } } /**