From patchwork Sun Aug 20 00:07:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 9910741 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EBB1E600C8 for ; Sun, 20 Aug 2017 00:06:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC13D28A62 for ; Sun, 20 Aug 2017 00:06:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CD46628A67; Sun, 20 Aug 2017 00:06:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8450328A62 for ; Sun, 20 Aug 2017 00:06:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752270AbdHTAGx (ORCPT ); Sat, 19 Aug 2017 20:06:53 -0400 Received: from mail-qt0-f196.google.com ([209.85.216.196]:33496 "EHLO mail-qt0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752241AbdHTAGw (ORCPT ); Sat, 19 Aug 2017 20:06:52 -0400 Received: by mail-qt0-f196.google.com with SMTP id 57so2414585qtu.0 for ; Sat, 19 Aug 2017 17:06:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=IqUDNZho0QqF/1nScb2pTKFyE2lZmLk/sXzt0pCTCdI=; b=VosfKsvQXlhB1cXHUjiC9CaP5CEz3jPZ3f9Kd8jRhZSfRHnDNVKFWrfCbsrV7L/3iZ LW96mFUCa+ekUo3IvCqhCMGxbuh66x4GHsz3tJtvrbECSE/PvaMKMrRRiIvsD4lI7IKZ KmAwMZ8Zp+fJfw6BcfdgAt06SqAjB0u4/37bMXbPo0zoGIlwQubR+diJKWPmT6SBpmTV C5IHLitNlHn6SJTjsFWJjJX7DfKkG8BKX9ieM9YM8L/JT1DwXy6yusntYVy0Kqy41DcC hfpFI9/GzG2iu60yZbQMPnve6dOZxeoLkM6Q+Gz1sSM5SO2G0we0uwbDhzXJT2Li8wJl o9Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=IqUDNZho0QqF/1nScb2pTKFyE2lZmLk/sXzt0pCTCdI=; b=G+FFWrIGePlJxizoQUjvdjZkwtW6ba38Hl5jdZFEmZoIe7BsERxMec4gQmd5HdepAM GWJvyfTWm5msza1j4Ss2Ztk6/1LeAfLAZ6XBcMQk17RQm89vGYkZZJy5yqg2Z6KcXVPc pT1ND6U9ZyIso96/wGIsLE8VsPzdun6HEdUKIm4m7CJyLDhlVf+VpmgYXkhn3wnLKN0q llVZpdwrFcdFWdPZyPOLzFg1+sINZrI/nhsw4UnAnWMJn6Pwtc0D9h8ttP+87YevFouD qQ9GcFhFB7ke8H1BmrB48OF9GxRPTPVzMw4wELgXSaVzdsHoqLoha0Dkg8h04b8/8SXb UaVg== X-Gm-Message-State: AHYfb5hZEx+iQUjHmaEFzLD/a+NhrMjPshzP5+NLmizTZ4kLZA6MWDK8 hro2jq3NcUmhjQ== X-Received: by 10.200.34.201 with SMTP id g9mr17919529qta.143.1503187611505; Sat, 19 Aug 2017 17:06:51 -0700 (PDT) Received: from localhost.localdomain ([201.82.170.189]) by smtp.gmail.com with ESMTPSA id v142sm424196qka.74.2017.08.19.17.06.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 19 Aug 2017 17:06:50 -0700 (PDT) From: Fabio Estevam To: bhelgaas@google.com Cc: heiko@sntech.de, linux-pci@vger.kernel.org, Fabio Estevam Subject: [PATCH] PCI: rockchip: Use gpiod_set_value_cansleep() to allow reset via expanders Date: Sat, 19 Aug 2017 21:07:14 -0300 Message-Id: <1503187634-3823-1-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 2.7.4 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The reset GPIO can be connected to a I2C or SPI IO expander, which may sleep, so it is safer to use the gpiod_set_value_cansleep() variant instead. Signed-off-by: Fabio Estevam --- drivers/pci/host/pcie-rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index 2eccd53..124b280 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -537,7 +537,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) int err, i; u32 status; - gpiod_set_value(rockchip->ep_gpio, 0); + gpiod_set_value_cansleep(rockchip->ep_gpio, 0); err = reset_control_assert(rockchip->aclk_rst); if (err) { @@ -682,7 +682,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, PCIE_CLIENT_CONFIG); - gpiod_set_value(rockchip->ep_gpio, 1); + gpiod_set_value_cansleep(rockchip->ep_gpio, 1); /* 500ms timeout value should be enough for Gen1/2 training */ err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,