From patchwork Sat Sep 23 07:24:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Wang X-Patchwork-Id: 9967409 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9B1DE602CB for ; Sat, 23 Sep 2017 07:25:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8D0F529A53 for ; Sat, 23 Sep 2017 07:25:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 81F8329A56; Sat, 23 Sep 2017 07:25:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 73EFB29A54 for ; Sat, 23 Sep 2017 07:25:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750831AbdIWHZV (ORCPT ); Sat, 23 Sep 2017 03:25:21 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:6555 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750762AbdIWHZV (ORCPT ); Sat, 23 Sep 2017 03:25:21 -0400 Received: from 172.30.72.58 (EHLO DGGEMS410-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DHW40890; Sat, 23 Sep 2017 15:25:18 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.301.0; Sat, 23 Sep 2017 15:25:08 +0800 From: Zhou Wang To: Bjorn Helgaas , CC: , Zhou Wang Subject: [RFC PATCH] PCI: Fix prefetchable range broken in pci_bridge_check_ranges Date: Sat, 23 Sep 2017 15:24:42 +0800 Message-ID: <1506151482-113560-1-git-send-email-wangzhou1@hisilicon.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.59C60C5E.0031, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: a9624cfc11138c7e57c950606ea93eaf Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When double checking 64bit prefetch range, we will change the prefetch range in a time slot by writing 0xffffffff to PCI_PREF_BASE_UPPER32. This may break transfers through related bridge at that time. E.g. if we have below PCIe topology: -[0000:00]-+-00.0-[01-02]--+-00.0 Device 8086:10fb | \-00.1 Device 8086:10fb \-08.0-[03]----00.0 Device 8086:0953 When rescan 00:08.0, it will call: pci_rescan_bus -> pci_assign_unassigned_bus_resources -> __pci_bus_size_bridges -> pci_bridge_check_ranges -> pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0xffffffff) This will change the prefetch range of 00:00.0 in a time slot, so traffic of 01:00.0 or 01:00.1 may be broken. In fact, we can get if one bridge supports 64bit range by the bottom 4bits of prefetchable memory base/limit. Honestly speaking, I don't know why 1f82de10d6b1 ("PCI/86: don't assume prefetchable ranges are 64bit") has added the double check code. So Can we remove the double checking of prefetchable range to avoid this problem? Signed-off-by: Zhou Wang --- drivers/pci/setup-bus.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 958da7d..23010a9 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -778,20 +778,6 @@ static void pci_bridge_check_ranges(struct pci_bus *bus) b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; } } - - /* double check if bridge does support 64 bit pref */ - if (b_res[2].flags & IORESOURCE_MEM_64) { - u32 mem_base_hi, tmp; - pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, - &mem_base_hi); - pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, - 0xffffffff); - pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); - if (!tmp) - b_res[2].flags &= ~IORESOURCE_MEM_64; - pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, - mem_base_hi); - } } /* Helper function for sizing routines: find first available