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Wed, 27 Sep 2017 18:20:48 +0000 From: Vadim Lomovtsev To: bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Wilson.Snyder@cavium.com, alex.williamson@redhat.com, Vadim Lomovtsev Subject: [PATCH v6] PCI: quirks: update Cavium ThunderX ACS quirk implementation Date: Wed, 27 Sep 2017 11:20:39 -0700 Message-Id: <1506536439-29318-1-git-send-email-Vadim.Lomovtsev@caviumnetworks.com> X-Mailer: git-send-email 2.4.11 In-Reply-To: <1506344920-24016-1-git-send-email-Vadim.Lomovtsev@caviumnetworks.com> References: <1506344920-24016-1-git-send-email-Vadim.Lomovtsev@caviumnetworks.com> MIME-Version: 1.0 X-Originating-IP: [50.233.148.156] X-ClientProxiedBy: BN6PR11CA0005.namprd11.prod.outlook.com (10.172.17.15) To CY4PR07MB3000.namprd07.prod.outlook.com (10.172.116.14) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7b361384-85ba-436b-56a4-08d505d47abb X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(2017030254152)(2017052603199)(201703131423075)(201703031133081)(201702281549075); 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However, the RTL internally implements similar protection as if ACS had completion/request redirection, upstream forwarding and validation features enabled. Current quirk implementation doesn't take into account PCIERCs which also needs to be quirked. So the pci device id check mask is updated and check of device ID moved into separate function. Signed-off-by: Vadim Lomovtsev Reviewed-by: Alex Williamson --- v5 -> v6: comment typo fix: change 0xa00 to 0xa000 drivers/pci/quirks.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index a4d3361..ed6c76d 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4211,20 +4211,33 @@ static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) #endif } -static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) +/* + * The Cavium downstream ports doesn't advertise their ACS capability registers. + * However, the RTL internally implements similar protection as if + * ACS had completion redirection, forwarding and validation features enabled. + * So by this flags we're asserting that the hardware implements and + * enables equivalent ACS functionality for these flags. + */ +#define CAVIUM_CN8XXX_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF) + +static __inline__ bool pci_quirk_cavium_acs_match(struct pci_dev *dev) { /* - * Cavium devices matching this quirk do not perform peer-to-peer - * with other functions, allowing masking out these bits as if they - * were unimplemented in the ACS capability. + * Effectively selects all downstream ports for whole ThunderX 1 family + * by 0xa000 mask (which represents 8 SoCs), while the lower bits of device ID + * are used to indicate which subdevice is used within the SoC. */ - acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | - PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); + return (pci_is_pcie(dev) && + (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) && + ((dev->device & 0xf800) == 0xa000)); +} - if (!((dev->device >= 0xa000) && (dev->device <= 0xa0ff))) +static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) +{ + if (!pci_quirk_cavium_acs_match(dev)) return -ENOTTY; - return acs_flags ? 0 : 1; + return acs_flags & ~(CAVIUM_CN8XXX_ACS_FLAGS) ? 0 : 1; } static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)