From patchwork Sat Sep 30 09:28:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhishek Shah X-Patchwork-Id: 9979331 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7038960375 for ; Sat, 30 Sep 2017 09:29:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 62E71295BD for ; Sat, 30 Sep 2017 09:29:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 57AEB295DD; Sat, 30 Sep 2017 09:29:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_HI,RCVD_IN_SORBS_SPAM autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0A887295BD for ; Sat, 30 Sep 2017 09:29:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752748AbdI3J3C (ORCPT ); Sat, 30 Sep 2017 05:29:02 -0400 Received: from mail-wr0-f174.google.com ([209.85.128.174]:52047 "EHLO mail-wr0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752741AbdI3J3B (ORCPT ); Sat, 30 Sep 2017 05:29:01 -0400 Received: by mail-wr0-f174.google.com with SMTP id j14so1059856wre.8 for ; Sat, 30 Sep 2017 02:29:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id; bh=2ST9+Pq1+tDpCOgviUf/jWVXef1k6wTNkXIRoP7DSb4=; b=NJdGNARg1JtgU3ffzeS3D4+TFA3g/GGMuPZ33tNAx6bL/nZdtdYk5S/KqYrzfOL5Bh Fqgc7fYaDeV0rt6eAq/ZM8icF4ylICxSk22KYFEirh51Y/vCfeF4hAzHZekTywYP6Lj4 63znz7hKF3Yr2cF2PkpHBCJbFn+DMnrY7pc5Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=2ST9+Pq1+tDpCOgviUf/jWVXef1k6wTNkXIRoP7DSb4=; b=uCajd/1auS9jbdmJX1qVA9xZuBjTMNy2tRbSl3X3d6jqukqttvV/64Q0LKfC7ZPcI0 AFL3sX5mG27WvWtY8oD4PsAxWwsJRfNOe7ZnFrNbEdQB0ilxPprhf3tjrA82QkewKvvk G7DDJLzYmsJ+zt4RW2XH3uJQ+36fF9+qzooaYX/kBr+Mfu1TjzZBQ+2AEquohMrp338o RaVwKfiMKSZhlE29yQez49GMstf8OwkUYqEpzjudt+AH7oBa7+/Qy7DwnOciqIrkQgTs vxVVGpPsZNK7hWS1G0QNWcTAFehbWX2fmlLrdARsMmMzQ+nkoKCbRmaLhhiJJA1JDU5H kCJA== X-Gm-Message-State: AHPjjUiWvkhDHFDWoev70az+cwA1sDW8dCteYXXbmhTo1SSDy681upb9 s1L8C/6pbzD6CjZZbWLlXWNEXQ== X-Google-Smtp-Source: AOwi7QC1k/JfoBvZ1gqTNmqI+vDSJX/8ymDcOcCGwjHuL7/6wg5H23VkTYYDjl4SfQVoRoLiiqP5XQ== X-Received: by 10.223.134.83 with SMTP id 19mr9069902wrw.223.1506763739976; Sat, 30 Sep 2017 02:28:59 -0700 (PDT) Received: from ashah1-OptiPlex-7010.dhcp.avagotech.net ([192.19.237.250]) by smtp.gmail.com with ESMTPSA id b190sm5286354wma.41.2017.09.30.02.28.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 30 Sep 2017 02:28:59 -0700 (PDT) From: Abhishek Shah To: Keith Busch , Jens Axboe , Christoph Hellwig , Sagi Grimberg Cc: linux-nvme@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, Abhishek Shah , stable@vger.kernel.org Subject: [PATCH v2] nvme-pci: Use PCI bus address for data/queues in CMB Date: Sat, 30 Sep 2017 14:58:42 +0530 Message-Id: <1506763722-10687-1-git-send-email-abhishek.shah@broadcom.com> X-Mailer: git-send-email 2.7.4 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, NVMe PCI host driver is programming CMB dma address as I/O SQs addresses. This results in failures on systems where 1:1 outbound mapping is not used (example Broadcom iProc SOCs) because CMB BAR will be progammed with PCI bus address but NVMe PCI EP will try to access CMB using dma address. To have CMB working on systems without 1:1 outbound mapping, we program PCI bus address for I/O SQs instead of dma address. This approach will work on systems with/without 1:1 outbound mapping. The patch is tested on Broadcom Stingray platform(arm64), which does not have 1:1 outbound mapping, as well as on x86 platform, which has 1:1 outbound mapping. Fixes: 8ffaadf7 ("NVMe: Use CMB for the IO SQes if available") Cc: stable@vger.kernel.org Signed-off-by: Abhishek Shah Reviewed-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- drivers/nvme/host/pci.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index 4a21213..1387050 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -94,6 +94,7 @@ struct nvme_dev { bool subsystem; void __iomem *cmb; dma_addr_t cmb_dma_addr; + pci_bus_addr_t cmb_bus_addr; u64 cmb_size; u32 cmbsz; u32 cmbloc; @@ -1220,7 +1221,7 @@ static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), dev->ctrl.page_size); - nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; + nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset; nvmeq->sq_cmds_io = dev->cmb + offset; } else { nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), @@ -1514,6 +1515,25 @@ static ssize_t nvme_cmb_show(struct device *dev, } static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); +static int nvme_find_cmb_bus_addr(struct pci_dev *pdev, + dma_addr_t dma_addr, + u64 size, + pci_bus_addr_t *bus_addr) +{ + struct resource *res; + struct pci_bus_region region; + struct resource tres = DEFINE_RES_MEM(dma_addr, size); + + res = pci_find_resource(pdev, &tres); + if (!res) + return -EIO; + + pcibios_resource_to_bus(pdev->bus, ®ion, res); + *bus_addr = region.start + (dma_addr - res->start); + + return 0; +} + static void __iomem *nvme_map_cmb(struct nvme_dev *dev) { u64 szu, size, offset; @@ -1547,6 +1567,9 @@ static void __iomem *nvme_map_cmb(struct nvme_dev *dev) size = bar_size - offset; dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; + if (nvme_find_cmb_bus_addr(pdev, dma_addr, size, &dev->cmb_bus_addr)) + return NULL; + cmb = ioremap_wc(dma_addr, size); if (!cmb) return NULL;