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Thu, 12 Oct 2017 04:40:55 +0000 (GMT) X-AuditID: b6c32a35-8adff70000001157-e5-59def257ef19 Received: from epmmp2 ( [203.254.227.17]) by epsmgms2p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 18.B8.06995.652FED95; Thu, 12 Oct 2017 13:40:54 +0900 (KST) Received: from ubuntu.sisodomain.com ([107.108.83.125]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OXP00668101H660@mmp2.samsung.com>; Thu, 12 Oct 2017 13:40:54 +0900 (KST) From: Pankaj Dubey To: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Joao Pinto , Pankaj Dubey Subject: [PATCH] PCI: designware: move dw_pcie_iatu_unroll_enabled to pcie-designware.c Date: Thu, 12 Oct 2017 10:11:08 +0530 Message-id: <1507783268-9022-1-git-send-email-pankaj.dubey@samsung.com> X-Mailer: git-send-email 2.7.4 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrJIsWRmVeSWpSXmKPExsWy7bCmnm74p3uRBve/GVgsacqwWPFlJrvF j0dHmS0uPO1hs7i8aw6bxdl5x9ksFm39wu7A7rFz1l12jwWbSj36tqxi9Niy/zOjx/Eb25k8 Pm+SC2CL4rJJSc3JLEst0rdL4MpY828Oe8Ef8Yp9n9axNDCuFOli5OSQEDCRWP7oNnMXIxeH kMAORokl71+wQTjfGSVWfG8HynCAVc1aVwYR38Ao8evLU3YI5yejRHvHLDaQUWwCuhJP3s9l BrFFBKwlGl6tYgUpYhY4yihxYOVeVpCEsECkxJxL7xhBbBYBVYnDn7rAmnkF3CXmTFjNCHGT nMTNc51gN0kI/GSVOP7gGQtEwkXiS+9GqCJhiVfHt7BDnCctcemoLUS4WuLJydcsEL0TGCU2 HjzODJGwlzhwZQ7YHGYBPol3X3tYIXp5JTrahCBKPCS6115ghAg7SmzeVgMSFhKIlbh19z7b BEbJBYwMqxjFUguKc9NTiw0LDPWKE3OLS/PS9ZLzczcxgiNQy3QH45RzPocYBTgYlXh4J2jc ixRiTSwrrsw9xCjBwawkwuu/CyjEm5JYWZValB9fVJqTWnyIUZqDRUmcV3T9tQghgfTEktTs 1NSC1CKYLBMHp1QDY2GFBevFk9eeh4ntuqhaxihotHeDX9B2tt2mijLXcxNdvNuaPHf9+fgm NojtqeDN3p2uM8+u9C3Zc4LVbX9c8ts13T2zFpjGndmpeetGxVqLy4pTLyypWmr7zueS6n7x a+v+R5SL3vO81hP6uP71r+2N5t37jxjsyti+Lzf1iyJjwbe3Ch9WKyqxFGckGmoxFxUnAgBI MKE0vAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrOJMWRmVeSWpSXmKPExsVy+t9jQd2wT/ciDe6+s7FY0pRhseLLTHaL H4+OMltceNrDZnF51xw2i7PzjrNZLNr6hd2B3WPnrLvsHgs2lXr0bVnF6LFl/2dGj+M3tjN5 fN4kF8AWxWWTkpqTWZZapG+XwJWx5t8c9oI/4hX7Pq1jaWBcKdLFyMEhIWAiMWtdWRcjF4eQ wDpGiTXtX9khnJ+MEl+PTmfpYuTkYBPQlXjyfi4ziC0iYC3R8GoVK0gRs8BRRomn044ygiSE BSIl5lx6B2azCKhKHP7UxQZi8wq4S8yZsBosLiEgJ3HzXCfzBEauBYwMqxglUwuKc9Nzi40K DPNSy/WKE3OLS/PS9ZLzczcxAoNj22Gtvh2M95fEH2IU4GBU4uF9oXUvUog1say4MvcQowQH s5IIr/8uoBBvSmJlVWpRfnxRaU5q8SFGaQ4WJXHe23nHIoUE0hNLUrNTUwtSi2CyTBycUkD/ /6mavlfrn9Oa+iq9n2ycK0uslpR8ksi+sbctK+CZXGL47Zi5hRdKuRgzdr6/w1l2L/Xqnush fV+Z3HYZXHU6JvxnYeXkbTXevvc6tiro7t36nePmxrM3Nn16ceXqw19Ky+yXpJdsN2eylBDr 5K1Tj2ZZcfvMppYDMWGv7oebei9lq7jUytGnxFKckWioxVxUnAgA1qMB5QoCAAA= X-CMS-MailID: 20171012044055epcas1p44b2e6b7cc21d42319529a518197aca9f X-Msg-Generator: CA X-Sender-IP: 182.195.42.142 X-Local-Sender: =?UTF-8?B?7YyQ7Lm07KaIG1NTSVItRkRTIFNXG+yCvOyEseyghOyekBsu?= =?UTF-8?B?L1NlbmlvciBDaGllZiBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?UEFOS0FKIEtVTUFSIERVQkVZG1NTSVItRkRTIFNXG1NhbXN1?= =?UTF-8?B?bmcgRWxlY3Ryb25pY3MbLi9TZW5pb3IgQ2hpZWYgRW5naW5lZXI=?= X-Sender-Code: =?UTF-8?B?QzEwG1NXQUhRG0MxMElEMDdJRDAxMDk5Nw==?= CMS-TYPE: 101P X-CMS-RootMailID: 20171012044055epcas1p44b2e6b7cc21d42319529a518197aca9f X-RootMTR: 20171012044055epcas1p44b2e6b7cc21d42319529a518197aca9f References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP IATU unroll feature can be enabled in EP mode as well, so we need to have this check in pcie-designware-ep.c, so instead of making this function as static in pcie-desigware-host.c, let's move this in pcie-designware.c so that both pcie-designware-host.c and pcie-designware-ep.c can use it. Signed-off-by: Pankaj Dubey Acked-by: Jingoo Han --- drivers/pci/dwc/pcie-designware-ep.c | 4 ++++ drivers/pci/dwc/pcie-designware-host.c | 11 ----------- drivers/pci/dwc/pcie-designware.c | 11 +++++++++++ drivers/pci/dwc/pcie-designware.h | 1 + 4 files changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c index d53d5f1..64803a9 100644 --- a/drivers/pci/dwc/pcie-designware-ep.c +++ b/drivers/pci/dwc/pcie-designware-ep.c @@ -314,6 +314,10 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) if (ep->ops->ep_init) ep->ops->ep_init(ep); + pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); + dev_dbg(dev, "iATU unroll: %s\n", + pci->iatu_unroll_enabled ? "enabled" : "disabled"); + epc = devm_pci_epc_create(dev, &epc_ops); if (IS_ERR(epc)) { dev_err(dev, "failed to create epc device\n"); diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c index 81e2157..d3f579e 100644 --- a/drivers/pci/dwc/pcie-designware-host.c +++ b/drivers/pci/dwc/pcie-designware-host.c @@ -574,17 +574,6 @@ static struct pci_ops dw_pcie_ops = { .write = dw_pcie_wr_conf, }; -static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) -{ - u32 val; - - val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); - if (val == 0xffffffff) - return 1; - - return 0; -} - void dw_pcie_setup_rc(struct pcie_port *pp) { u32 val; diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index 88abddd..f15da90 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -92,6 +92,17 @@ void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, dev_err(pci->dev, "write DBI address failed\n"); } +u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) +{ + u32 val; + + val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); + if (val == 0xffffffff) + return 1; + + return 0; +} + static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h index e5d9d77..8d6829c 100644 --- a/drivers/pci/dwc/pcie-designware.h +++ b/drivers/pci/dwc/pcie-designware.h @@ -242,6 +242,7 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar, void dw_pcie_disable_atu(struct dw_pcie *pci, int index, enum dw_pcie_region_type type); void dw_pcie_setup(struct dw_pcie *pci); +u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci); static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) {