From patchwork Fri Oct 27 19:29:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 10030489 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B222A6022E for ; Fri, 27 Oct 2017 19:31:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9478428FFD for ; Fri, 27 Oct 2017 19:31:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8937128FDF; Fri, 27 Oct 2017 19:31:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 07ED628FFB for ; Fri, 27 Oct 2017 19:31:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932237AbdJ0TbQ (ORCPT ); Fri, 27 Oct 2017 15:31:16 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17938 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932315AbdJ0TbM (ORCPT ); Fri, 27 Oct 2017 15:31:12 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 27 Oct 2017 12:30:47 -0700 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 27 Oct 2017 12:31:14 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 27 Oct 2017 12:31:14 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 27 Oct 2017 19:30:55 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Fri, 27 Oct 2017 19:30:55 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 27 Oct 2017 12:30:55 -0700 From: Manikanta Maddireddy To: , , CC: , , , , Manikanta Maddireddy Subject: [PATCH 11/12] PCI: tegra: Increase the deskew retry time Date: Sat, 28 Oct 2017 00:59:28 +0530 Message-ID: <1509132569-9398-12-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509132569-9398-1-git-send-email-mmaddireddy@nvidia.com> References: <1509132569-9398-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some times Gen2 to Gen1 link speed switching fails due to instability in deskew logic on lane0 in Tegra210. Increase the deskew retry time to resolve this issue. Signed-off-by: Manikanta Maddireddy --- drivers/pci/host/pci-tegra.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 9680bf7d0a95..db1ce74ba64a 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -222,6 +222,10 @@ #define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) #define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18) +#define RP_VEND_CTL0 0xf44 +#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12) +#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH (0x9 << 12) + #define RP_VEND_CTL1 0xf48 #define RP_VEND_CTL1_ERPT (1 << 13) @@ -316,6 +320,7 @@ struct tegra_pcie_soc { bool program_ectl_settings; bool update_clamp_threshold; bool RAW_violation_fixup; + bool program_deskew_time; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2214,6 +2219,16 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK; writel(value, port->base + RP_VEND_XP); } + + /* Tune deskew retry time to take care of Gen2 -> Gen1 + * link speed change error in corner cases + */ + if (soc->program_deskew_time) { + value = readl(port->base + RP_VEND_CTL0); + value &= ~RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK; + value |= RP_VEND_CTL0_DSK_RST_PULSE_WIDTH; + writel(value, port->base + RP_VEND_CTL0); + } } /* * FIXME: If there are no PCIe cards attached, then calling this function @@ -2352,6 +2367,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .program_ectl_settings = false, .update_clamp_threshold = false, .RAW_violation_fixup = false, + .program_deskew_time = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2371,6 +2387,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .program_ectl_settings = false, .update_clamp_threshold = false, .RAW_violation_fixup = false, + .program_deskew_time = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2389,6 +2406,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .program_ectl_settings = false, .update_clamp_threshold = true, .RAW_violation_fixup = true, + .program_deskew_time = false, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2415,6 +2433,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .program_ectl_settings = true, .update_clamp_threshold = true, .RAW_violation_fixup = false, + .program_deskew_time = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2434,6 +2453,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .program_ectl_settings = false, .update_clamp_threshold = false, .RAW_violation_fixup = false, + .program_deskew_time = false, }; static const struct of_device_id tegra_pcie_of_match[] = {