From patchwork Fri Oct 27 19:29:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 10030491 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9061F6022E for ; Fri, 27 Oct 2017 19:31:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 72FE528FE2 for ; Fri, 27 Oct 2017 19:31:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 715A028FDF; Fri, 27 Oct 2017 19:31:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0886F28FE2 for ; Fri, 27 Oct 2017 19:31:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932364AbdJ0TbR (ORCPT ); Fri, 27 Oct 2017 15:31:17 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:19669 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932312AbdJ0TbQ (ORCPT ); Fri, 27 Oct 2017 15:31:16 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Fri, 27 Oct 2017 12:30:55 -0700 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 27 Oct 2017 12:30:54 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 27 Oct 2017 12:30:54 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 27 Oct 2017 19:30:28 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Fri, 27 Oct 2017 19:30:28 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 27 Oct 2017 12:30:28 -0700 From: Manikanta Maddireddy To: , , CC: , , , , Manikanta Maddireddy Subject: [PATCH 04/12] PCI: tegra: Advertise AER capability Date: Sat, 28 Oct 2017 00:59:21 +0530 Message-ID: <1509132569-9398-5-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509132569-9398-1-git-send-email-mmaddireddy@nvidia.com> References: <1509132569-9398-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Default root port settings hide AER capability. This patch enables the advertisement of AER capability by root port. Signed-off-by: Manikanta Maddireddy --- drivers/pci/host/pci-tegra.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 15df60e13a14..c0cd88103e9e 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -187,6 +187,9 @@ #define RP_VEND_XP 0x00000f00 #define RP_VEND_XP_DL_UP (1 << 30) +#define RP_VEND_CTL1 0xf48 +#define RP_VEND_CTL1_ERPT (1 << 13) + #define RP_VEND_CTL2 0x00000fa8 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) @@ -2055,6 +2058,16 @@ static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie) pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); } +static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) +{ + unsigned long value; + + /* Enable AER capability */ + value = readl(port->base + RP_VEND_CTL1); + value |= RP_VEND_CTL1_ERPT; + writel(value, port->base + RP_VEND_CTL1); +} + /* * FIXME: If there are no PCIe cards attached, then calling this function * can result in the increase of the bootup time as there are big timeout @@ -2119,6 +2132,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) port->index, port->lanes); tegra_pcie_port_enable(port); + tegra_pcie_enable_rp_features(port); } /* take the PCIe interface module out of reset */