From patchwork Fri Oct 27 19:29:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 10030485 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CFDDA6022E for ; Fri, 27 Oct 2017 19:31:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B250528FF5 for ; Fri, 27 Oct 2017 19:31:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B0ACD28E1C; Fri, 27 Oct 2017 19:31:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 16CBB28FD9 for ; Fri, 27 Oct 2017 19:31:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932343AbdJ0TbN (ORCPT ); Fri, 27 Oct 2017 15:31:13 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17930 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932244AbdJ0TbM (ORCPT ); Fri, 27 Oct 2017 15:31:12 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 27 Oct 2017 12:30:47 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 27 Oct 2017 12:31:04 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 27 Oct 2017 12:31:04 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 27 Oct 2017 19:30:40 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 27 Oct 2017 19:30:40 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Fri, 27 Oct 2017 19:30:40 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 27 Oct 2017 12:30:40 -0700 From: Manikanta Maddireddy To: , , CC: , , , , Manikanta Maddireddy Subject: [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating Date: Sat, 28 Oct 2017 00:59:24 +0530 Message-ID: <1509132569-9398-8-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509132569-9398-1-git-send-email-mmaddireddy@nvidia.com> References: <1509132569-9398-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When there are 32 outstanding writes from AFI to memory, the outstanding write counter overflows and indicates that there are "0" outstanding write transactions. This outstanding write counter is used to generate IDLE signal to dynamically gate the AFI clock. When memory controller is under heavy load, its possible that write completions will come back to AFI after long delay and AFI write counter overflows. AFI clock gets gated even when there are outstanding transactions towards memory controller resutling in system hang. Disable dynamic clock gating of AFI clock to avoid system hang. Signed-off-by: Manikanta Maddireddy --- drivers/pci/host/pci-tegra.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 27a8211c48b2..b8cac871712b 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -103,8 +103,9 @@ #define AFI_MSI_EN_VEC6 0xa4 #define AFI_MSI_EN_VEC7 0xa8 -#define AFI_CONFIGURATION 0xac -#define AFI_CONFIGURATION_EN_FPCI (1 << 0) +#define AFI_CONFIGURATION 0xac +#define AFI_CONFIGURATION_EN_FPCI (1 << 0) +#define AFI_CONFIGURATION_CLKEN_OVERRIDE (1 << 31) #define AFI_FPCI_ERROR_MASKS 0xb0 @@ -1057,9 +1058,10 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) } } - /* finally enable PCIe */ + /* Disable AFI dynamic clock gating and enable PCIe */ value = afi_readl(pcie, AFI_CONFIGURATION); - value |= AFI_CONFIGURATION_EN_FPCI; + value |= (AFI_CONFIGURATION_EN_FPCI | + AFI_CONFIGURATION_CLKEN_OVERRIDE); afi_writel(pcie, value, AFI_CONFIGURATION); value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |