From patchwork Mon Oct 30 04:18:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 10032047 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7C995603B4 for ; Mon, 30 Oct 2017 04:21:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6CAEC28724 for ; Mon, 30 Oct 2017 04:21:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 60069286B7; Mon, 30 Oct 2017 04:21:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D8B14286B7 for ; Mon, 30 Oct 2017 04:21:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751347AbdJ3EVw (ORCPT ); Mon, 30 Oct 2017 00:21:52 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:13972 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751209AbdJ3EVw (ORCPT ); Mon, 30 Oct 2017 00:21:52 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Sun, 29 Oct 2017 21:21:30 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 29 Oct 2017 21:21:48 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 29 Oct 2017 21:21:48 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:19:55 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 04:19:55 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 29 Oct 2017 21:19:54 -0700 From: Manikanta Maddireddy To: , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V2 03/12] PCI: tegra: Retrain link for Gen2 speed Date: Mon, 30 Oct 2017 09:48:54 +0530 Message-ID: <1509337143-25963-4-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> References: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra124, 132, 210 and 186 supports Gen2 link speed. After the link is up in Gen1, set target link speed as Gen2 and retrain link. Link switches to Gen2 speed if Gen2 capable end point is connected, else link stays in Gen1. Signed-off-by: Manikanta Maddireddy --- V2: * Fixed alignment issue drivers/pci/host/pci-tegra.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 2c64eb6cc3cc..9f6d331c3571 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -232,6 +232,8 @@ #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ +#define LINK_RETRAIN_TIMEOUT HZ + struct tegra_msi { struct msi_controller chip; DECLARE_BITMAP(used, INT_PCI_MSI_NR); @@ -2133,6 +2135,42 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) } } +static void tegra_pcie_change_link_speed(struct tegra_pcie *pcie, + struct pci_dev *pci_dev) +{ + struct device *dev = pcie->dev; + unsigned long start_jiffies; + unsigned short val; + + /* Skip if the current device is not a root port */ + if (pci_pcie_type(pci_dev) != PCI_EXP_TYPE_ROOT_PORT) + return; + + pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL2, &val); + val &= ~PCI_EXP_LNKSTA_CLS; + val |= PCI_EXP_LNKSTA_CLS_5_0GB; + pcie_capability_write_word(pci_dev, PCI_EXP_LNKCTL2, val); + + /* Retrain the link */ + pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL, &val); + val |= PCI_EXP_LNKCTL_RL; + pcie_capability_write_word(pci_dev, PCI_EXP_LNKCTL, val); + + start_jiffies = jiffies; + for (;;) { + pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &val); + if (!(val & PCI_EXP_LNKSTA_LT)) + break; + if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) + break; + usleep_range(2000, 3000); + } + + if (val & PCI_EXP_LNKSTA_LT) + dev_err(dev, "link retrain of PCIe slot %u failed\n", + PCI_SLOT(pci_dev->devfn)); +} + static const struct tegra_pcie_soc tegra20_pcie = { .num_ports = 2, .msi_base_shift = 0, @@ -2334,6 +2372,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) struct pci_host_bridge *host; struct tegra_pcie *pcie; struct pci_bus *child; + struct pci_dev *pci_dev = NULL; int err; host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); @@ -2399,6 +2438,9 @@ static int tegra_pcie_probe(struct platform_device *pdev) pci_bus_add_devices(host->bus); + for_each_pci_dev(pci_dev) + tegra_pcie_change_link_speed(pcie, pci_dev); + if (IS_ENABLED(CONFIG_DEBUG_FS)) { err = tegra_pcie_debugfs_init(pcie); if (err < 0)