From patchwork Mon Oct 30 13:57:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 10032695 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AC94660291 for ; Mon, 30 Oct 2017 14:01:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B14FB288D9 for ; Mon, 30 Oct 2017 14:01:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A6402288DE; Mon, 30 Oct 2017 14:01:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 29DFD288D9 for ; Mon, 30 Oct 2017 14:01:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752455AbdJ3OBF (ORCPT ); Mon, 30 Oct 2017 10:01:05 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:18606 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752053AbdJ3OBE (ORCPT ); Mon, 30 Oct 2017 10:01:04 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 30 Oct 2017 07:00:34 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 07:00:53 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 30 Oct 2017 07:00:53 -0700 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:58:50 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 13:58:50 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 06:58:50 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 12/12] PCI: tegra: Update flow control threshold in Tegra210 Date: Mon, 30 Oct 2017 19:27:23 +0530 Message-ID: <1509371843-22931-13-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> References: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Recommended update FC threshold in Tegra210 is 0x60 for best performance of x1 link. Setting this to 0x60 provides the best balance between number of UpdateFC and read data sent over the link. Signed-off-by: Manikanta Maddireddy --- V3: * changed soc parameter name V2: * no change in this patch drivers/pci/host/pci-tegra.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index b29329226e3d..812d32cfdd0e 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -223,6 +223,7 @@ #define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27) #define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) #define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18) +#define RP_VEND_XP_UPDATE_FC_THRESHOLD_T210 (0x60 << 18) #define RP_VEND_CTL0 0xf44 #define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12) @@ -323,6 +324,7 @@ struct tegra_pcie_soc { bool update_clamp_threshold; bool raw_violation_fixup; bool program_deskew_time; + bool update_fc_threshold; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2231,6 +2233,13 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) value |= RP_VEND_CTL0_DSK_RST_PULSE_WIDTH; writel(value, port->base + RP_VEND_CTL0); } + + if (soc->update_fc_threshold) { + value = readl(port->base + RP_VEND_XP); + value &= ~RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK; + value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_T210; + writel(value, port->base + RP_VEND_XP); + } } /* * FIXME: If there are no PCIe cards attached, then calling this function @@ -2371,6 +2380,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .update_clamp_threshold = false, .raw_violation_fixup = false, .program_deskew_time = false, + .update_fc_threshold = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2391,6 +2401,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .update_clamp_threshold = false, .raw_violation_fixup = false, .program_deskew_time = false, + .update_fc_threshold = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2410,6 +2421,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .update_clamp_threshold = true, .raw_violation_fixup = true, .program_deskew_time = false, + .update_fc_threshold = false, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2437,6 +2449,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .update_clamp_threshold = true, .raw_violation_fixup = false, .program_deskew_time = true, + .update_fc_threshold = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2457,6 +2470,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .update_clamp_threshold = false, .raw_violation_fixup = false, .program_deskew_time = false, + .update_fc_threshold = false, }; static const struct of_device_id tegra_pcie_of_match[] = {