From patchwork Fri Dec 22 05:39:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Honghui Zhang X-Patchwork-Id: 10128801 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AE2C26019C for ; Fri, 22 Dec 2017 05:40:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9D0FB29EAD for ; Fri, 22 Dec 2017 05:40:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F18329FC3; Fri, 22 Dec 2017 05:40:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 30BAE29EAD for ; Fri, 22 Dec 2017 05:40:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751912AbdLVFkC (ORCPT ); Fri, 22 Dec 2017 00:40:02 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:54415 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751631AbdLVFj5 (ORCPT ); Fri, 22 Dec 2017 00:39:57 -0500 X-UUID: 76b614985eff442383735b383da4bd39-20171222 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1339828862; Fri, 22 Dec 2017 13:39:52 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 22 Dec 2017 13:39:50 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 22 Dec 2017 13:39:50 +0800 From: To: , , , , , , , , , , CC: , , , , , , Subject: [PATCH v4 1/2] PCI: mediatek: Clear IRQ status after IRQ dispatched to avoid reentry Date: Fri, 22 Dec 2017 13:39:37 +0800 Message-ID: <1513921178-16148-2-git-send-email-honghui.zhang@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1513921178-16148-1-git-send-email-honghui.zhang@mediatek.com> References: <1513921178-16148-1-git-send-email-honghui.zhang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Honghui Zhang There maybe a same IRQ reentry scenario after IRQ received in current IRQ handle flow: EP device PCIe host driver EP driver 1. issue an IRQ 2. received IRQ 3. clear IRQ status 4. dispatch IRQ 5. clear IRQ source The IRQ status was not successfully cleared at step 2 since the IRQ source was not cleared yet. So the PCIe host driver may receive the same IRQ after step 5. Then there's an IRQ reentry occurred. Even worse, if the reentry IRQ was not an IRQ that EP driver expected, it may not handle the IRQ. Then we may run into the infinite loop from step 2 to step 4. Clear the IRQ status after IRQ have been dispatched to avoid the IRQ reentry. This patch also fix another INTx IRQ issue by initialize the iterate before the loop. If an INTx IRQ re-occurred while we are dispatching the INTx IRQ, then iterate may start from PCI_NUM_INTX + INTX_SHIFT instead of INTX_SHIFT for the second time entering the for_each_set_bit_from() loop. Signed-off-by: Honghui Zhang Acked-by: Ryder Lee --- drivers/pci/host/pcie-mediatek.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c index db93efd..fc29a9a 100644 --- a/drivers/pci/host/pcie-mediatek.c +++ b/drivers/pci/host/pcie-mediatek.c @@ -601,15 +601,16 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data) struct mtk_pcie_port *port = (struct mtk_pcie_port *)data; unsigned long status; u32 virq; - u32 bit = INTX_SHIFT; + u32 bit; while ((status = readl(port->base + PCIE_INT_STATUS)) & INTX_MASK) { + bit = INTX_SHIFT; for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { - /* Clear the INTx */ - writel(1 << bit, port->base + PCIE_INT_STATUS); virq = irq_find_mapping(port->irq_domain, bit - INTX_SHIFT); generic_handle_irq(virq); + /* Clear the INTx */ + writel(1 << bit, port->base + PCIE_INT_STATUS); } } @@ -619,10 +620,10 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data) while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) { - /* Clear the MSI */ - writel(1 << bit, port->base + PCIE_IMSI_STATUS); virq = irq_find_mapping(port->msi_domain, bit); generic_handle_irq(virq); + /* Clear the MSI */ + writel(1 << bit, port->base + PCIE_IMSI_STATUS); } } /* Clear MSI interrupt status */