From patchwork Fri Mar 23 07:47:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 10302885 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 288C360386 for ; Fri, 23 Mar 2018 07:54:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1B29F28C6E for ; Fri, 23 Mar 2018 07:54:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0EA0C28C70; Fri, 23 Mar 2018 07:54:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.4 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_WEB autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6CFAB28C6E for ; Fri, 23 Mar 2018 07:54:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751471AbeCWHyy (ORCPT ); Fri, 23 Mar 2018 03:54:54 -0400 Received: from lucky1.263xmail.com ([211.157.147.130]:57618 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751395AbeCWHyy (ORCPT ); Fri, 23 Mar 2018 03:54:54 -0400 Received: from shawn.lin?rock-chips.com (unknown [192.168.167.233]) by lucky1.263xmail.com (Postfix) with ESMTP id 960441F5A83; Fri, 23 Mar 2018 15:54:44 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id A69763D6; Fri, 23 Mar 2018 15:54:41 +0800 (CST) X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: bhelgaas@google.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <8996981b321c707f233ca76a0adfef1e> X-ATTACHMENT-NUM: 0 X-SENDER: lintao@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 41481J19NV; Fri, 23 Mar 2018 15:54:42 +0800 (CST) From: Shawn Lin To: Bjorn Helgaas , Lorenzo Pieralisi Cc: linux-rockchip@lists.infradead.org, linux-pci@vger.kernel.org, Shawn Lin Subject: [PATCH] PCI: rockchip: Fix compile errors and warnings Date: Fri, 23 Mar 2018 15:47:59 +0800 Message-Id: <1521791279-148357-1-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.9.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP pcie-rockchip.c uses devm_pci_remap_cfg_resource which should depends on CONFIG_PCI. And as we could allow to build the host driver as a module, we should export the function. This patch also make rockchip_pcie_{prog, clear}_ep_ob_atu static. Reported-by: kbuild test robot Fixes: 52f3757afc06 ("PCI: rockchip: Create individual folder for rockchip drivers"); Fixes: 7257f9f50c02 ("PCI: rockchip: Add Endpoint controller driver for Rockchip PCIe controller") Signed-off-by: Shawn Lin --- drivers/pci/rockchip/Kconfig | 1 + drivers/pci/rockchip/pcie-rockchip-ep.c | 10 ++++++---- drivers/pci/rockchip/pcie-rockchip.c | 7 +++++++ 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/pci/rockchip/Kconfig b/drivers/pci/rockchip/Kconfig index 668f850..f4ac165 100644 --- a/drivers/pci/rockchip/Kconfig +++ b/drivers/pci/rockchip/Kconfig @@ -4,6 +4,7 @@ menu "Rockchip PCIe controllers support" config PCIE_ROCKCHIP bool + depends on PCI config PCIE_ROCKCHIP_HOST tristate "Rockchip PCIe host controller" diff --git a/drivers/pci/rockchip/pcie-rockchip-ep.c b/drivers/pci/rockchip/pcie-rockchip-ep.c index 01997ce..8aa31a3 100644 --- a/drivers/pci/rockchip/pcie-rockchip-ep.c +++ b/drivers/pci/rockchip/pcie-rockchip-ep.c @@ -49,7 +49,8 @@ struct rockchip_pcie_ep { u8 irq_pending; }; -void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip, u32 region) +static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip, + u32 region) { rockchip_pcie_write(rockchip, 0, ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(region)); @@ -65,9 +66,10 @@ void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip, u32 region) ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(region)); } -void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, - u32 r, u32 type, u64 cpu_addr, u64 pci_addr, - size_t size) +static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, + u32 r, u32 type, u64 cpu_addr, + u64 pci_addr, + size_t size) { u64 sz = 1ULL << fls64(size - 1); int num_pass_bits = ilog2(sz); diff --git a/drivers/pci/rockchip/pcie-rockchip.c b/drivers/pci/rockchip/pcie-rockchip.c index 9071178..9025a81 100644 --- a/drivers/pci/rockchip/pcie-rockchip.c +++ b/drivers/pci/rockchip/pcie-rockchip.c @@ -151,6 +151,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) return 0; } +EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt); int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) { @@ -291,6 +292,7 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) phy_exit(rockchip->phys[i]); return err; } +EXPORT_SYMBOL_GPL(rockchip_pcie_init_port); int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip) { @@ -332,6 +334,7 @@ int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip) return 0; } +EXPORT_SYMBOL_GPL(rockchip_pcie_get_phys); void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip) { @@ -344,6 +347,7 @@ void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip) phy_exit(rockchip->phys[i]); } } +EXPORT_SYMBOL_GPL(rockchip_pcie_deinit_phys); int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip) { @@ -384,6 +388,7 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip) clk_disable_unprepare(rockchip->aclk_pcie); return err; } +EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks); void rockchip_pcie_disable_clocks(void *data) { @@ -394,6 +399,7 @@ void rockchip_pcie_disable_clocks(void *data) clk_disable_unprepare(rockchip->aclk_perf_pcie); clk_disable_unprepare(rockchip->aclk_pcie); } +EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks); void rockchip_pcie_cfg_configuration_accesses( struct rockchip_pcie *rockchip, u32 type) @@ -414,3 +420,4 @@ void rockchip_pcie_cfg_configuration_accesses( rockchip_pcie_write(rockchip, ob_desc_0, PCIE_CORE_OB_REGION_DESC0); rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1); } +EXPORT_SYMBOL_GPL(rockchip_pcie_cfg_configuration_accesses);