From patchwork Mon May 7 08:52:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Subrahmanya Lingappa X-Patchwork-Id: 10383691 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CD8F260159 for ; Mon, 7 May 2018 08:53:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C127028A25 for ; Mon, 7 May 2018 08:53:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B5DFB28A28; Mon, 7 May 2018 08:53:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_WEB autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BEBFA28A29 for ; Mon, 7 May 2018 08:53:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752015AbeEGIxB (ORCPT ); Mon, 7 May 2018 04:53:01 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:41405 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751977AbeEGIxA (ORCPT ); Mon, 7 May 2018 04:53:00 -0400 Received: by mail-pg0-f65.google.com with SMTP id m21-v6so19744438pgv.8 for ; Mon, 07 May 2018 01:52:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mobiveil.co.in; s=google; h=from:to:cc:subject:date:message-id; bh=h4LXnJJrIkAE3bvaidX1H1LY8ulMMhqcpO0M66tAPJg=; b=jtDLTO1pDstHJn0AqOwllNNoZj5BFDLw3QaISAOeGNXnExxILYbdC0ITWS6Lt2qSvg VZN1Od5gdaU8F5FFy8xkjNxqvjntixAEgziIrrnB+0EQd1DeDHyir/ldKd4ckNNDEoRe sgVlXZ6mvrnNx9+sPG1DR/GhBySIDe5p17OYM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=h4LXnJJrIkAE3bvaidX1H1LY8ulMMhqcpO0M66tAPJg=; b=V33IHi0eWA9/j07HF/R8jBWnpNArWFrCeY6feZ9ZxOnWEu2UwASqdfc+JLVwx+g5QB Ntmr0xQsUWfafJgwNctxrjoTd6Lu1e6EkMgMg4LUZ4vWOOn+lzYavkHRR/X0Gcj7qUUw j2EZ3i7cltxKBGw7DM+IwhkIKB17OEGpQexWbwBTPwnXj33P5JLMWl2KTY0yu98SBvOk YV70HdRam5lHq8zGNUpM8GUQFTKLBagQWajWq3WI10A6eyDvafj2n8JtUIsnzOdKdc20 IgqsdxZ2/SBILgQcMdIMUiCefZff/7kVG91wZBFJC3Pu/29rngxnK84gylbDPTJJcA2d HgJw== X-Gm-Message-State: ALQs6tBY3dvdal17XKdruNAVT2wL5A5PnG/1bt9ms9o1fC15cBE7Djaq FfdQm8VWs6U/tHptLa00SvGAyJn5 X-Google-Smtp-Source: AB8JxZo02xP+FZXP77npIKP6JPcpnVwZY9l+nhduDJ6+WVHhyq4jJOjRmWUTz1hF4dimKB6POuvp2Q== X-Received: by 2002:a17:902:9a49:: with SMTP id x9-v6mr36269363plv.94.1525683179085; Mon, 07 May 2018 01:52:59 -0700 (PDT) Received: from localhost.localdomain.localdomain ([106.51.19.61]) by smtp.gmail.com with ESMTPSA id z8-v6sm27405375pgc.13.2018.05.07.01.52.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 07 May 2018 01:52:58 -0700 (PDT) From: Subrahmanya Lingappa To: linux-pci@vger.kernel.org, bhelgaas@google.com, lorenzo.pieralisi@arm.com, marc.zyngier@arm.com Cc: mingkai.hu@nxp.com, peter.newton@nxp.com, minghuan.lian@nxp.com, rajesh.raina@nxp.com, rajan.kapoor@nxp.com, prabhjot.singh@nxp.com, Subrahmanya Lingappa Subject: [PATCH v10 3/3] PCI: mobiveil: Add MSI support Date: Mon, 7 May 2018 04:52:51 -0400 Message-Id: <1525683171-9674-1-git-send-email-l.subrahmanya@mobiveil.co.in> X-Mailer: git-send-email 1.8.3.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Implement MSI support for Mobiveil PCIe Host Bridge IP device driver. Signed-off-by: Subrahmanya Lingappa Cc: Bjorn Helgaas Cc: Lorenzo Pieralisi Cc: Marc Zyngier Cc: linux-pci@vger.kernel.org --- drivers/pci/host/pcie-mobiveil.c | 209 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 202 insertions(+), 7 deletions(-) diff --git a/drivers/pci/host/pcie-mobiveil.c b/drivers/pci/host/pcie-mobiveil.c index 02b1f5d..2b67a2e 100644 --- a/drivers/pci/host/pcie-mobiveil.c +++ b/drivers/pci/host/pcie-mobiveil.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -56,6 +57,7 @@ #define PAB_INTP_AMBA_MISC_ENB 0x0b0c #define PAB_INTP_AMBA_MISC_STAT 0x0b1c #define PAB_INTP_INTX_MASK 0x1e0 +#define PAB_INTP_MSI_MASK 0x8 #define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win) #define WIN_ENABLE_SHIFT 0 @@ -84,7 +86,18 @@ #define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win) /* supported number of interrupts */ -#define PAB_INTX_START 5 +#define PAB_INTX_START 5 +#define PCI_NUM_MSI 16 + +/* MSI registers */ +#define MSI_BASE_LO_OFFSET 0x04 +#define MSI_BASE_HI_OFFSET 0x08 +#define MSI_SIZE_OFFSET 0x0c +#define MSI_ENABLE_OFFSET 0x14 +#define MSI_STATUS_OFFSET 0x18 +#define MSI_DATA_OFFSET 0x20 +#define MSI_ADDR_L_OFFSET 0x24 +#define MSI_ADDR_H_OFFSET 0x28 /* outbound and inbound window definitions */ #define WIN_NUM_0 0 @@ -97,14 +110,24 @@ /* Parameters for the waiting for link up routine */ #define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_MIN 90000 -#define LINK_WAIT_MAX 100000 +#define LINK_WAIT_MIN 90000 +#define LINK_WAIT_MAX 100000 + +struct mobiveil_msi { /* MSI information */ + struct mutex lock; /* protect bitmap variable */ + struct irq_domain *msi_domain; + struct irq_domain *dev_domain; + phys_addr_t msi_pages_phys; + int num_of_vectors; + DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI); +}; struct mobiveil_pcie { struct platform_device *pdev; struct list_head resources; void __iomem *config_axi_slave_base; /* endpoint config base */ void __iomem *csr_axi_slave_base; /* root port config base */ + void __iomem *apb_csr_base; /* MSI register base */ void __iomem *pcie_reg_base; /* Physical PCIe Controller Base */ struct irq_domain *intx_domain; raw_spinlock_t intx_mask_lock; @@ -115,6 +138,7 @@ struct mobiveil_pcie { int ib_wins_configured; /* configured inbound windows */ struct resource *ob_io_res; char root_bus_nr; + struct mobiveil_msi msi; }; static inline void csr_writel(struct mobiveil_pcie *pcie, const u32 value, @@ -194,13 +218,15 @@ static void mobiveil_pcie_isr(struct irq_desc *desc) struct irq_chip *chip = irq_desc_get_chip(desc); struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); struct device *dev = &pcie->pdev->dev; - u32 intr_status; + struct mobiveil_msi *msi = &pcie->msi; + u32 msi_data, msi_addr_lo, msi_addr_hi; + u32 intr_status, msi_status; unsigned long shifted_status; u32 bit, virq, val, mask; /* - * The core provides interrupt for INTx. - * So we'll read INTx status. + * The core provides a single interrupt for both INTx/MSI messages. + * So we'll read both INTx and MSI status */ chained_irq_enter(chip, desc); @@ -232,6 +258,35 @@ static void mobiveil_pcie_isr(struct irq_desc *desc) } while ((shifted_status >> PAB_INTX_START) != 0); } + /* read extra MSI status register */ + msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET); + + /* handle MSI interrupts */ + while (msi_status & 1) { + msi_data = readl_relaxed(pcie->apb_csr_base + + MSI_DATA_OFFSET); + + /* + * MSI_STATUS_OFFSET register gets updated to zero + * once we pop not only the MSI data but also address + * from MSI hardware FIFO. So keeping these following + * two dummy reads. + */ + msi_addr_lo = readl_relaxed(pcie->apb_csr_base + + MSI_ADDR_L_OFFSET); + msi_addr_hi = readl_relaxed(pcie->apb_csr_base + + MSI_ADDR_H_OFFSET); + dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n", + msi_data, msi_addr_hi, msi_addr_lo); + + virq = irq_find_mapping(msi->dev_domain, msi_data); + if (virq) + generic_handle_irq(virq); + + msi_status = readl_relaxed(pcie->apb_csr_base + + MSI_STATUS_OFFSET); + } + /* Clear the interrupt status */ csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT); chained_irq_exit(chip, desc); @@ -267,6 +322,12 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) return PTR_ERR(pcie->csr_axi_slave_base); pcie->pcie_reg_base = res->start; + /* map MSI config resource */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr"); + pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pcie->apb_csr_base)) + return PTR_ERR(pcie->apb_csr_base); + /* read the number of windows requested */ if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins)) pcie->apio_wins = MAX_PIO_WINDOWS; @@ -416,6 +477,22 @@ static int mobiveil_bringup_link(struct mobiveil_pcie *pcie) return -ETIMEDOUT; } +static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie) +{ + phys_addr_t msg_addr = pcie->pcie_reg_base; + struct mobiveil_msi *msi = &pcie->msi; + + pcie->msi.num_of_vectors = PCI_NUM_MSI; + msi->msi_pages_phys = (phys_addr_t)msg_addr; + + writel_relaxed(lower_32_bits(msg_addr), + pcie->apb_csr_base + MSI_BASE_LO_OFFSET); + writel_relaxed(upper_32_bits(msg_addr), + pcie->apb_csr_base + MSI_BASE_HI_OFFSET); + writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET); + writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET); +} + static int mobiveil_host_init(struct mobiveil_pcie *pcie) { u32 value, pab_ctrl, type = 0; @@ -445,7 +522,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) (1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL); - csr_writel(pcie, (PAB_INTP_INTX_MASK), + csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), PAB_INTP_AMBA_MISC_ENB); /* @@ -485,6 +562,9 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) } } + /* setup MSI hardware registers */ + mobiveil_pcie_enable_msi(pcie); + return err; } @@ -540,6 +620,116 @@ static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq, .map = mobiveil_pcie_intx_map, }; +static struct irq_chip mobiveil_msi_irq_chip = { + .name = "Mobiveil PCIe MSI", + .irq_mask = pci_msi_mask_irq, + .irq_unmask = pci_msi_unmask_irq, +}; + +static struct msi_domain_info mobiveil_msi_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX), + .chip = &mobiveil_msi_irq_chip, +}; + +static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) +{ + struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data); + phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int)); + + msg->address_lo = lower_32_bits(addr); + msg->address_hi = upper_32_bits(addr); + msg->data = data->hwirq; + + dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n", + (int)data->hwirq, msg->address_hi, msg->address_lo); +} + +static int mobiveil_msi_set_affinity(struct irq_data *irq_data, + const struct cpumask *mask, bool force) +{ + return -EINVAL; +} + +static struct irq_chip mobiveil_msi_bottom_irq_chip = { + .name = "Mobiveil MSI", + .irq_compose_msi_msg = mobiveil_compose_msi_msg, + .irq_set_affinity = mobiveil_msi_set_affinity, +}; + +static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, void *args) +{ + struct mobiveil_pcie *pcie = domain->host_data; + struct mobiveil_msi *msi = &pcie->msi; + unsigned long bit; + + WARN_ON(nr_irqs != 1); + mutex_lock(&msi->lock); + + bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors); + if (bit >= msi->num_of_vectors) { + mutex_unlock(&msi->lock); + return -ENOSPC; + } + + set_bit(bit, msi->msi_irq_in_use); + + mutex_unlock(&msi->lock); + + irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip, + domain->host_data, handle_level_irq, + NULL, NULL); + return 0; +} + +static void mobiveil_irq_msi_domain_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d); + struct mobiveil_msi *msi = &pcie->msi; + + mutex_lock(&msi->lock); + + if (!test_bit(d->hwirq, msi->msi_irq_in_use)) { + dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n", + d->hwirq); + } else { + __clear_bit(d->hwirq, msi->msi_irq_in_use); + } + + mutex_unlock(&msi->lock); +} +static const struct irq_domain_ops msi_domain_ops = { + .alloc = mobiveil_irq_msi_domain_alloc, + .free = mobiveil_irq_msi_domain_free, +}; + +static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie) +{ + struct device *dev = &pcie->pdev->dev; + struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); + struct mobiveil_msi *msi = &pcie->msi; + + mutex_init(&pcie->msi.lock); + msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors, + &msi_domain_ops, pcie); + if (!msi->dev_domain) { + dev_err(dev, "failed to create IRQ domain\n"); + return -ENOMEM; + } + + msi->msi_domain = pci_msi_create_irq_domain(fwnode, + &mobiveil_msi_domain_info, msi->dev_domain); + if (!msi->msi_domain) { + dev_err(dev, "failed to create MSI domain\n"); + irq_domain_remove(msi->dev_domain); + return -ENOMEM; + } + return 0; +} + static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie) { struct device *dev = &pcie->pdev->dev; @@ -557,6 +747,11 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie) raw_spin_lock_init(&pcie->intx_mask_lock); + /* setup MSI */ + ret = mobiveil_allocate_msi_domains(pcie); + if (ret) + return ret; + return 0; }