From patchwork Mon Oct 15 08:08:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Honghui Zhang X-Patchwork-Id: 10641249 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9F9BE157A for ; Mon, 15 Oct 2018 08:09:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9286429443 for ; Mon, 15 Oct 2018 08:09:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 86C2429454; Mon, 15 Oct 2018 08:09:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2D36D29443 for ; Mon, 15 Oct 2018 08:09:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726877AbeJOPxa (ORCPT ); Mon, 15 Oct 2018 11:53:30 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:5739 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726541AbeJOPx3 (ORCPT ); Mon, 15 Oct 2018 11:53:29 -0400 X-UUID: eb559fd023654af18dd01ec0cff9cea7-20181015 X-UUID: eb559fd023654af18dd01ec0cff9cea7-20181015 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 2098282582; Mon, 15 Oct 2018 16:09:12 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Oct 2018 16:09:04 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 15 Oct 2018 16:09:03 +0800 From: To: , , , , , , CC: , , , , , , , , , , Subject: [PATCH v8 2/9] PCI: mediatek: Fix class type for MT7622 as PCI_CLASS_BRIDGE_PCI Date: Mon, 15 Oct 2018 16:08:53 +0800 Message-ID: <1539590940-13355-3-git-send-email-honghui.zhang@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1539590940-13355-1-git-send-email-honghui.zhang@mediatek.com> References: <1539590940-13355-1-git-send-email-honghui.zhang@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 728839C9B44E609B6062AB040177C67E0A3995E05C615B527F71B1440D4657B62000:8 X-MTK: N Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Honghui Zhang The commit 101c92dc80c8 ("PCI: mediatek: Set up vendor ID and class type for MT7622") have set the class type for MT7622 as un-properly value of PCI_CLASS_BRIDGE_HOST. The PCIe controller of MT7622 is complexed with Root Port and PCI-to-PCI bridge, the bridge has type 1 configuration space header and related bridge windows. The HW default value of this bridge's class type is invalid. Fix its class type as PCI_CLASS_BRIDGE_PCI since it is HW defines. Making the bridge visiable to PCI framework by setting its class type properly will get its bridge windows configurated during PCI device enumerate. Fixes: 101c92dc80c8 ("PCI: mediatek: Set up vendor ID and class type for MT7622") Signed-off-by: Honghui Zhang Acked-by: Ryder Lee --- drivers/pci/controller/pcie-mediatek.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index 288b8e2..bcdac9b 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -432,7 +432,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) val = PCI_VENDOR_ID_MEDIATEK; writew(val, port->base + PCIE_CONF_VEND_ID); - val = PCI_CLASS_BRIDGE_HOST; + val = PCI_CLASS_BRIDGE_PCI; writew(val, port->base + PCIE_CONF_CLASS_ID); }