| Message ID | 1546409810-37630-3-git-send-email-ley.foon.tan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | Add Stratix 10 PCIe Root Port support | expand |
On Wed, 2 Jan 2019 14:16:49 +0800, Ley Foon Tan wrote: > Add support for altr,pcie-root-port-2.0. > > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> > --- > .../devicetree/bindings/pci/altera-pcie.txt | 4 +++- > 1 files changed, 3 insertions(+), 1 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt index 6c396f1..816b244 100644 --- a/Documentation/devicetree/bindings/pci/altera-pcie.txt +++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt @@ -1,11 +1,13 @@ * Altera PCIe controller Required properties: -- compatible : should contain "altr,pcie-root-port-1.0" +- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0" - reg: a list of physical base address and length for TXS and CRA. + For "altr,pcie-root-port-2.0", additional HIP base address and length. - reg-names: must include the following entries: "Txs": TX slave port region "Cra": Control register access region + "Hip": Hard IP region (if "altr,pcie-root-port-2.0") - interrupts: specifies the interrupt source of the parent interrupt controller. The format of the interrupt specifier depends on the parent interrupt controller.
Add support for altr,pcie-root-port-2.0. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> --- .../devicetree/bindings/pci/altera-pcie.txt | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-)