| Message ID | 1568118302-10505-2-git-send-email-pankaj.dubey@samsung.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | [1/2] PCI: dwc: Add support to disable GEN3 equalization | expand |
On Tue, Sep 10, 2019 at 05:55:02PM +0530, Pankaj Dubey wrote: > From: Anvesh Salveru <anvesh.s@samsung.com> > > In some platforms, PCIe PHY may have issues which will prevent linkup > to happen in GEN3 or high speed. In case equalization fails, link will > fallback to GEN1. > > Designware controller gives flexibility to disable GEN3 equalization > completely or only phase 2 and 3. Do some platforms have issues conducting phase 2 and 3 when they successfully conduct phase 0 and 1? > > Platform drivers can disable equalization phase 2 and 3, by setting > dwc_pci_quirk flag DWC_EQUALIZATION_DISABLE. > > Signed-off-by: Anvesh Salveru <anvesh.s@samsung.com> > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> > --- > drivers/pci/controller/dwc/pcie-designware.c | 3 +++ > drivers/pci/controller/dwc/pcie-designware.h | 2 ++ > 2 files changed, 5 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index bf82091..97a8268 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -472,5 +472,8 @@ void dw_pcie_setup(struct dw_pcie *pci) > if (pci->dwc_pci_quirk & DWC_EQUALIZATION_DISABLE) > val |= PORT_LOGIC_GEN3_EQ_DISABLE; > > + if (pci->dwc_pci_quirk & DWC_EQ_PHASE_2_3_DISABLE) > + val |= PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE; > + > dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); > } > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index a1453c5..b541508 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -31,6 +31,7 @@ > > /* Parameters for PCIe Quirks */ > #define DWC_EQUALIZATION_DISABLE 0x1 > +#define DWC_EQ_PHASE_2_3_DISABLE 0x2 It only makes sense for either DWC_EQUALIZATION_DISABLE or DWC_EQ_PHASE_2_3_DISABLE to be specified, though if dwc_pci_quirk intends to hold other quirks should these be numbers and not bit fields? Thanks, Andrew Murray > > /* Synopsys-specific PCIe configuration registers */ > #define PCIE_PORT_LINK_CONTROL 0x710 > @@ -65,6 +66,7 @@ > > #define PCIE_PORT_GEN3_RELATED 0x890 > #define PORT_LOGIC_GEN3_EQ_DISABLE BIT(16) > +#define PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE BIT(9) > > #define PCIE_ATU_VIEWPORT 0x900 > #define PCIE_ATU_REGION_INBOUND BIT(31) > -- > 2.7.4 >
On Tue, 10 Sep 2019 at 19:59, Andrew Murray <andrew.murray@arm.com> wrote: > > On Tue, Sep 10, 2019 at 05:55:02PM +0530, Pankaj Dubey wrote: > > From: Anvesh Salveru <anvesh.s@samsung.com> > > > > In some platforms, PCIe PHY may have issues which will prevent linkup > > to happen in GEN3 or high speed. In case equalization fails, link will > > fallback to GEN1. > > > > Designware controller gives flexibility to disable GEN3 equalization > > completely or only phase 2 and 3. > > Do some platforms have issues conducting phase 2 and 3 when they successfully > conduct phase 0 and 1? > Yes, it is possible. > > > > Platform drivers can disable equalization phase 2 and 3, by setting > > dwc_pci_quirk flag DWC_EQUALIZATION_DISABLE. > > > > Signed-off-by: Anvesh Salveru <anvesh.s@samsung.com> > > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> > > --- > > drivers/pci/controller/dwc/pcie-designware.c | 3 +++ > > drivers/pci/controller/dwc/pcie-designware.h | 2 ++ > > 2 files changed, 5 insertions(+) > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > > index bf82091..97a8268 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > @@ -472,5 +472,8 @@ void dw_pcie_setup(struct dw_pcie *pci) > > if (pci->dwc_pci_quirk & DWC_EQUALIZATION_DISABLE) > > val |= PORT_LOGIC_GEN3_EQ_DISABLE; > > > > + if (pci->dwc_pci_quirk & DWC_EQ_PHASE_2_3_DISABLE) > > + val |= PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE; > > + > > dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); > > } > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > > index a1453c5..b541508 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.h > > +++ b/drivers/pci/controller/dwc/pcie-designware.h > > @@ -31,6 +31,7 @@ > > > > /* Parameters for PCIe Quirks */ > > #define DWC_EQUALIZATION_DISABLE 0x1 > > +#define DWC_EQ_PHASE_2_3_DISABLE 0x2 > > It only makes sense for either DWC_EQUALIZATION_DISABLE or DWC_EQ_PHASE_2_3_DISABLE > to be specified, though if dwc_pci_quirk intends to hold other quirks should these > be numbers and not bit fields? > Yes, you are right in a given platform it will be either DWC_EQUALIZATION_DISABLE or DWC_EQ_PHASE_2_3_DISABLE. Intention behind making it bit-field was to add other quirks in future. > Thanks, > > Andrew Murray > > > > > /* Synopsys-specific PCIe configuration registers */ > > #define PCIE_PORT_LINK_CONTROL 0x710 > > @@ -65,6 +66,7 @@ > > > > #define PCIE_PORT_GEN3_RELATED 0x890 > > #define PORT_LOGIC_GEN3_EQ_DISABLE BIT(16) > > +#define PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE BIT(9) > > > > #define PCIE_ATU_VIEWPORT 0x900 > > #define PCIE_ATU_REGION_INBOUND BIT(31) > > -- > > 2.7.4 > >
On Tue, Sep 10, 2019 at 09:51:41PM +0530, Pankaj Dubey wrote: > On Tue, 10 Sep 2019 at 19:59, Andrew Murray <andrew.murray@arm.com> wrote: > > > > On Tue, Sep 10, 2019 at 05:55:02PM +0530, Pankaj Dubey wrote: > > > From: Anvesh Salveru <anvesh.s@samsung.com> > > > > > > In some platforms, PCIe PHY may have issues which will prevent linkup > > > to happen in GEN3 or high speed. In case equalization fails, link will > > > fallback to GEN1. > > > > > > Designware controller gives flexibility to disable GEN3 equalization > > > completely or only phase 2 and 3. > > > > Do some platforms have issues conducting phase 2 and 3 when they successfully > > conduct phase 0 and 1? > > > > Yes, it is possible. > > > > > > > Platform drivers can disable equalization phase 2 and 3, by setting > > > dwc_pci_quirk flag DWC_EQUALIZATION_DISABLE. > > > > > > Signed-off-by: Anvesh Salveru <anvesh.s@samsung.com> > > > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> > > > --- > > > drivers/pci/controller/dwc/pcie-designware.c | 3 +++ > > > drivers/pci/controller/dwc/pcie-designware.h | 2 ++ > > > 2 files changed, 5 insertions(+) > > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > > > index bf82091..97a8268 100644 > > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > > @@ -472,5 +472,8 @@ void dw_pcie_setup(struct dw_pcie *pci) > > > if (pci->dwc_pci_quirk & DWC_EQUALIZATION_DISABLE) > > > val |= PORT_LOGIC_GEN3_EQ_DISABLE; > > > > > > + if (pci->dwc_pci_quirk & DWC_EQ_PHASE_2_3_DISABLE) > > > + val |= PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE; > > > + Also is it harmless to set both DWC_EQUALIZATION_DISABLE and DWC_EQ_PHASE_2_3_DISABLE? (Which is permitted here). Thanks, Andrew Murray > > > dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); > > > } > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > > > index a1453c5..b541508 100644 > > > --- a/drivers/pci/controller/dwc/pcie-designware.h > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h > > > @@ -31,6 +31,7 @@ > > > > > > /* Parameters for PCIe Quirks */ > > > #define DWC_EQUALIZATION_DISABLE 0x1 > > > +#define DWC_EQ_PHASE_2_3_DISABLE 0x2 > > > > It only makes sense for either DWC_EQUALIZATION_DISABLE or DWC_EQ_PHASE_2_3_DISABLE > > to be specified, though if dwc_pci_quirk intends to hold other quirks should these > > be numbers and not bit fields? > > > Yes, you are right in a given platform it will be either > DWC_EQUALIZATION_DISABLE or DWC_EQ_PHASE_2_3_DISABLE. > > Intention behind making it bit-field was to add other quirks in future. > > > Thanks, > > > > Andrew Murray > > > > > > > > /* Synopsys-specific PCIe configuration registers */ > > > #define PCIE_PORT_LINK_CONTROL 0x710 > > > @@ -65,6 +66,7 @@ > > > > > > #define PCIE_PORT_GEN3_RELATED 0x890 > > > #define PORT_LOGIC_GEN3_EQ_DISABLE BIT(16) > > > +#define PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE BIT(9) > > > > > > #define PCIE_ATU_VIEWPORT 0x900 > > > #define PCIE_ATU_REGION_INBOUND BIT(31) > > > -- > > > 2.7.4 > > >
> From: Andrew Murray <andrew.murray@arm.com> > > On Tue, Sep 10, 2019 at 09:51:41PM +0530, Pankaj Dubey wrote: > > On Tue, 10 Sep 2019 at 19:59, Andrew Murray <andrew.murray@arm.com> > wrote: > > > > > > On Tue, Sep 10, 2019 at 05:55:02PM +0530, Pankaj Dubey wrote: > > > > From: Anvesh Salveru <anvesh.s@samsung.com> > > > > > > > > In some platforms, PCIe PHY may have issues which will prevent > > > > linkup to happen in GEN3 or high speed. In case equalization > > > > fails, link will fallback to GEN1. > > > > > > > > Designware controller gives flexibility to disable GEN3 > > > > equalization completely or only phase 2 and 3. > > > > > > Do some platforms have issues conducting phase 2 and 3 when they > > > successfully conduct phase 0 and 1? > > > > > > > Yes, it is possible. > > > > > > > > > > Platform drivers can disable equalization phase 2 and 3, by > > > > setting dwc_pci_quirk flag DWC_EQUALIZATION_DISABLE. > > > > > > > > Signed-off-by: Anvesh Salveru <anvesh.s@samsung.com> > > > > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> > > > > --- > > > > drivers/pci/controller/dwc/pcie-designware.c | 3 +++ > > > > drivers/pci/controller/dwc/pcie-designware.h | 2 ++ > > > > 2 files changed, 5 insertions(+) > > > > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c > > > > b/drivers/pci/controller/dwc/pcie-designware.c > > > > index bf82091..97a8268 100644 > > > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > > > @@ -472,5 +472,8 @@ void dw_pcie_setup(struct dw_pcie *pci) > > > > if (pci->dwc_pci_quirk & DWC_EQUALIZATION_DISABLE) > > > > val |= PORT_LOGIC_GEN3_EQ_DISABLE; > > > > > > > > + if (pci->dwc_pci_quirk & DWC_EQ_PHASE_2_3_DISABLE) > > > > + val |= PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE; > > > > + > > Also is it harmless to set both DWC_EQUALIZATION_DISABLE and > DWC_EQ_PHASE_2_3_DISABLE? (Which is permitted here). > Yes, it will be harmless. > Thanks, > > Andrew Murray > > > > > dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); } > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h > > > > b/drivers/pci/controller/dwc/pcie-designware.h > > > > index a1453c5..b541508 100644 > > > > --- a/drivers/pci/controller/dwc/pcie-designware.h > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h > > > > @@ -31,6 +31,7 @@ > > > > > > > > /* Parameters for PCIe Quirks */ > > > > #define DWC_EQUALIZATION_DISABLE 0x1 > > > > +#define DWC_EQ_PHASE_2_3_DISABLE 0x2 > > > > > > It only makes sense for either DWC_EQUALIZATION_DISABLE or > > > DWC_EQ_PHASE_2_3_DISABLE to be specified, though if dwc_pci_quirk > > > intends to hold other quirks should these be numbers and not bit fields? > > > > > Yes, you are right in a given platform it will be either > > DWC_EQUALIZATION_DISABLE or DWC_EQ_PHASE_2_3_DISABLE. > > > > Intention behind making it bit-field was to add other quirks in future. > > > > > Thanks, > > > > > > Andrew Murray > > > > > > > > > > > /* Synopsys-specific PCIe configuration registers */ > > > > #define PCIE_PORT_LINK_CONTROL 0x710 > > > > @@ -65,6 +66,7 @@ > > > > > > > > #define PCIE_PORT_GEN3_RELATED 0x890 > > > > #define PORT_LOGIC_GEN3_EQ_DISABLE BIT(16) > > > > +#define PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE BIT(9) > > > > > > > > #define PCIE_ATU_VIEWPORT 0x900 > > > > #define PCIE_ATU_REGION_INBOUND BIT(31) > > > > -- > > > > 2.7.4 > > > >
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index bf82091..97a8268 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -472,5 +472,8 @@ void dw_pcie_setup(struct dw_pcie *pci) if (pci->dwc_pci_quirk & DWC_EQUALIZATION_DISABLE) val |= PORT_LOGIC_GEN3_EQ_DISABLE; + if (pci->dwc_pci_quirk & DWC_EQ_PHASE_2_3_DISABLE) + val |= PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE; + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index a1453c5..b541508 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -31,6 +31,7 @@ /* Parameters for PCIe Quirks */ #define DWC_EQUALIZATION_DISABLE 0x1 +#define DWC_EQ_PHASE_2_3_DISABLE 0x2 /* Synopsys-specific PCIe configuration registers */ #define PCIE_PORT_LINK_CONTROL 0x710 @@ -65,6 +66,7 @@ #define PCIE_PORT_GEN3_RELATED 0x890 #define PORT_LOGIC_GEN3_EQ_DISABLE BIT(16) +#define PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE BIT(9) #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND BIT(31)