| Message ID | 1581574091-240890-2-git-send-email-shawn.lin@rock-chips.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | Add Rockchip new PCIe controller and combo phy support | expand |
On Thu, 13 Feb 2020 14:08:06 +0800, Shawn Lin wrote: > This IP could supports USB3.0 and PCIe. > > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> > > --- > > Changes in v2: > - fix yaml format > > .../bindings/phy/rockchip,inno-combophy.yaml | 80 ++++++++++++++++++++++ > 1 file changed, 80 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml > My bot found errors running 'make dt_binding_check' on your patch: Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node Error: Documentation/devicetree/bindings/phy/rockchip,inno-combophy.example.dts:21.28-29 syntax error FATAL ERROR: Unable to parse input tree scripts/Makefile.lib:300: recipe for target 'Documentation/devicetree/bindings/phy/rockchip,inno-combophy.example.dt.yaml' failed make[1]: *** [Documentation/devicetree/bindings/phy/rockchip,inno-combophy.example.dt.yaml] Error 1 Makefile:1263: recipe for target 'dt_binding_check' failed make: *** [dt_binding_check] Error 2 See https://patchwork.ozlabs.org/patch/1237296 Please check and re-submit.
Hi Shawn, Am Donnerstag, 13. Februar 2020, 07:08:06 CET schrieb Shawn Lin: > This IP could supports USB3.0 and PCIe. > > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> > > --- > > Changes in v2: > - fix yaml format > > .../bindings/phy/rockchip,inno-combophy.yaml | 80 ++++++++++++++++++++++ can we make this rockchip,inno-usb3pciephy or something similar please? Same for the driver name. -combophy is completely non-descriptive and looking at the Rockchip vendor-tree we already have: - phy-rockchip-inno-combphy.c (this one) - phy-rockchip-inno-mipi-dphy.c (rk1808 dsi, but should actually fit into combo) - phy-rockchip-inno-video-combo-phy.c (dsi/lvds/ttl) - phy-rockchip-inno-video-phy.c (rk3288-lvds) All of them have quite none-descriptive names The inno-video-combo-phy already got a somewhat nicer name in mainline (dsidphy), so I think it would be cool to also do this here (and for the driver of course). > + reset-names: > + items: > + - const: otg-rst > + - const: combphy-por > + - const: combphy-apb > + - const: combphy-pipe reset-names are local to the node, so there is no need for combophy prefixes, so these should probably be: - const: otg-rst - const: por - const: apb - const: pipe > + > + rockchip,combphygrf: > + enum: > + - rockchip,combphygrf nicer name here? :-) Thanks Heiko
diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml new file mode 100644 index 0000000..841f88a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,inno-combophy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip USB3.0/PCI-e combo phy + +maintainers: + - Shawn Lin <shawn.lin@rock-chips.com> + - William Wu <william.wu@rock-chips.com> + +properties: + "#phy-cells": + const: 1 + + compatible: + enum: + - rockchip,rk1808-combphy + + reg: + maxItems: 1 + + clocks: + items: + - description: PLL reference clock + + clock-names: + items: + - const: refclk + + resets: + items: + - description: OTG unit reset line + - description: POR unit reset line + - description: APB interface reset line + - description: PIPE unit reset line + + reset-names: + items: + - const: otg-rst + - const: combphy-por + - const: combphy-apb + - const: combphy-pipe + + rockchip,combphygrf: + enum: + - rockchip,combphygrf + description: The grf for COMBPHY configuration and state registers. + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - rockchip,combphygrf + +additionalProperties: false + +examples: + - | + combphy: phy@ff380000 { + compatible = "rockchip,rk1808-combphy"; + reg = <0x0 0xff380000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + assigned-clock-rates = <25000000>; + resets = <&cru SRST_USB3_OTG_A>, <&cru SRST_PCIEPHY_POR>, + <&cru SRST_PCIEPHY_P>, <&cru SRST_PCIEPHY_PIPE>; + reset-names = "otg-rst", "combphy-por", + "combphy-apb", "combphy-pipe"; + rockchip,combphygrf = <&combphy_grf>; + }; + +...
This IP could supports USB3.0 and PCIe. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- Changes in v2: - fix yaml format .../bindings/phy/rockchip,inno-combophy.yaml | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml