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Thu, 7 May 2020 04:59:38 -0700 Received: from [10.140.9.2] (helo=xhdbharatku40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1jWfBh-00081d-Ff; Thu, 07 May 2020 04:59:37 -0700 From: Bharat Kumar Gogada To: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh@kernel.org, rgummal@xilinx.com, Bharat Kumar Gogada Subject: [PATCH v7 1/2] PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port Date: Thu, 7 May 2020 17:28:35 +0530 Message-Id: <1588852716-23132-2-git-send-email-bharat.kumar.gogada@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1588852716-23132-1-git-send-email-bharat.kumar.gogada@xilinx.com> References: <1588852716-23132-1-git-send-email-bharat.kumar.gogada@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapsmtpgw01;PTR:unknown-60-83.xilinx.com;CAT:NONE;SFTY:;SFS:(346002)(376002)(136003)(39860400002)(396003)(46966005)(33430700001)(70586007)(26005)(478600001)(2616005)(966005)(336012)(316002)(70206006)(47076004)(426003)(8936002)(33440700001)(4326008)(7696005)(82740400003)(8676002)(36756003)(186003)(82310400002)(81166007)(2906002)(107886003)(9786002)(5660300002)(356005);DIR:OUT;SFP:1101; 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Signed-off-by: Bharat Kumar Gogada --- .../devicetree/bindings/pci/xilinx-versal-cpm.yaml | 105 +++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml new file mode 100644 index 0000000..5fc5c3f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CPM Host Controller device tree for Xilinx Versal SoCs + +maintainers: + - Bharat Kumar Gogada + +properties: + compatible: + const: xlnx,versal-cpm-host-1.00 + + "#address-cells": + const: 3 + + "#size-cells": + const: 2 + + reg: + items: + - description: Configuration space region and bridge registers. + - description: CPM system level control and status registers. + + reg-names: + items: + - const: cfg + - const: cpm_slcr + + interrupts: + maxItems: 1 + + msi-map: + description: + Maps a Requester ID to an MSI controller and associated MSI sideband data. + + ranges: + maxItems: 2 + + "#interrupt-cells": + const: 1 + + interrupt-map-mask: + description: Standard PCI IRQ mapping properties. + + interrupt-map: + description: Standard PCI IRQ mapping properties. + + interrupt_controller: + description: Interrupt controller child node. + + bus-range: + description: Range of bus numbers associated with this controller. + +required: + - compatible + - "#address-cells" + - "#size-cells" + - reg + - reg-names + - "#interrupt-cells" + - interrupts + - interrupt-parent + - interrupt-map + - interrupt-map-mask + - ranges + - bus-range + - msi-map + +additionalProperties: false + +examples: + - | + + versal { + #address-cells = <2>; + #size-cells = <2>; + cpm_pcie: pci@fca10000 { + compatible = "xlnx,versal-cpm-host-1.00"; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + interrupts = <0 72 4>; + interrupt-parent = <&gic>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, + <0 0 0 2 &pcie_intc_0 1>, + <0 0 0 3 &pcie_intc_0 2>, + <0 0 0 4 &pcie_intc_0 3>; + bus-range = <0x00 0xff>; + ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, + <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; + msi-map = <0x0 &its_gic 0x0 0x10000>; + reg = <0x6 0x00000000 0x0 0x10000000>, + <0x0 0xfca10000 0x0 0x1000>; + reg-names = "cfg", "cpm_slcr"; + pcie_intc_0: interrupt_controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller ; + }; + }; + };