From patchwork Thu Sep 10 01:39:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "tiantao (H)" X-Patchwork-Id: 11766425 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1369859D for ; Thu, 10 Sep 2020 02:52:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F419521D81 for ; Thu, 10 Sep 2020 02:52:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730244AbgIJB60 (ORCPT ); Wed, 9 Sep 2020 21:58:26 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:38792 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729717AbgIJBmA (ORCPT ); Wed, 9 Sep 2020 21:42:00 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 1F70173F049F34145939; Thu, 10 Sep 2020 09:41:53 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.487.0; Thu, 10 Sep 2020 09:41:46 +0800 From: Tian Tao To: , , , , , CC: Subject: [PATCH] PCI: dwc: Do not export local function dw_pcie_link_set_max_speed Date: Thu, 10 Sep 2020 09:39:26 +0800 Message-ID: <1599701966-38778-1-git-send-email-tiantao6@hisilicon.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org WARNING: modpost: "dw_pcie_link_set_max_speed" [vmlinux] is a static EXPORT_SYMBOL_GPL Fixes: 3af45d34d30c ("PCI: dwc: Centralize link gen setting") Signed-off-by: Tian Tao --- drivers/pci/controller/dwc/pcie-designware.c | 1 - mm/madvise.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 4d105ef..3c3a4d1 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -508,7 +508,6 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen) dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed); } -EXPORT_SYMBOL_GPL(dw_pcie_link_set_max_speed); static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) { diff --git a/mm/madvise.c b/mm/madvise.c index c5acc2b..8c175f9 100644 --- a/mm/madvise.c +++ b/mm/madvise.c @@ -30,7 +30,6 @@ #include #include #include -#include #include