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Thu, 7 Jan 2021 15:30:28 +0000 (GMT) From: Shradha Todi To: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org Cc: pankaj.dubey@samsung.com, sriram.dash@samsung.com, niyas.ahmed@samsung.com, p.rajanbabu@samsung.com, l.mehra@samsung.com, hari.tv@samsung.com, Anvesh Salveru , Shradha Todi , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas Subject: [PATCH v7 2/5] PCI: dwc: add support to handle ZRX-DC Compliant PHYs Date: Thu, 7 Jan 2021 20:58:40 +0530 Message-Id: <1610033323-10560-3-git-send-email-shradha.t@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1610033323-10560-1-git-send-email-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprBKsWRmVeSWpSXmKPExsWy7bCmhm6J0fd4gz2HTSx+rJ7AbLGkKcNi 190OdouP01YyWaz4MpPd4s7zG4wWl3fNYbM4O+84m0Xnl1lsFm9+v2C3eDLlEavF0Y3BFou2 fmG3+L9nB7tF7+Faixvr2R0EPNbMW8PosXPWXXaPBZtKPTat6mTz6NuyitFjy/7PjB6fN8kF sEdx2aSk5mSWpRbp2yVwZSw9285SsFek4sme20wNjIcFuxg5OSQETCSWzFnE2MXIxSEksJtR Yu73pVDOJ0aJxi9fmSCcz4wSZ/5+Z4RpubvpDjNEYhdQ4tEvVginhUlixaJrTCBVbAJaEo1f u5hBbBGBKImZ21vBipgFtjFLTNs+lRUkISzgL7Hl7zUWEJtFQFXiVetLMJtXwFXi1d0b7BDr 5CRunusEG8Qp4Cbxbdo6sEESAlM5JBbvPgJ1k4vEm19/mSFsYYlXx7dANUtJfH63lw3CzpeY euEp0AIOILtCYnlPHUTYXuLAlTlgYWYBTYn1u/QhwrISU0+tA/uFWYBPovf3EyaIOK/Ejnkw trLEl797WCBsSYl5xy6zQtgeEp0/Z0KDbiajxL+miywTGOVmIaxYwMi4ilEytaA4Nz212LTA OC+1XK84Mbe4NC9dLzk/dxMjOPFoee9gfPTgg94hRiYOxkOMEhzMSiK8Fse+xAvxpiRWVqUW 5ccXleakFh9ilOZgURLn3WHwIF5IID2xJDU7NbUgtQgmy8TBKdXA9OxrR7nNi9+LeZuei2w4 /vqgytm/bCkOWU7KXtfXTnpfGR38zmR1d2030/o675m7y/bteZJwZkbyxk7vYyWXKytd3kvb 1JzbHpZ8fW/FjrIvM5z4rL/9/JG72mV2XWBv8XzJJXWuS3n17W6cOdf317Hoo7SC6FGef0e2 MH0XaTFXebz8lZnF/Rlnw/M2ZpcdueBf/pZz9sJZX7fPZl/6TseJ+dS+bIe5xnMsP79tan2l uiw+t3ND+9qm5GoTQ/1Tuu3TmcvCZkxbwqLuLOXTwFV4rjr3Cff/nFUqDgsfM8XKzzA7c2D+ t3mHi6+/vq5326fuq0bzvK6ze33iP+xxS31wyvGl+B+N2NiMxRFtlUosxRmJhlrMRcWJANbm fRWrAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrJLMWRmVeSWpSXmKPExsWy7bCSvK6Y5vd4g5YpxhY/Vk9gtljSlGGx 624Hu8XHaSuZLFZ8mclucef5DUaLy7vmsFmcnXeczaLzyyw2ize/X7BbPJnyiNXi6MZgi0Vb v7Bb/N+zg92i93CtxY317A4CHmvmrWH02DnrLrvHgk2lHptWdbJ59G1ZxeixZf9nRo/Pm+QC 2KO4bFJSczLLUov07RK4MpaebWcp2CtS8WTPbaYGxsOCXYycHBICJhJ3N91h7mLk4hAS2MEo cWhmLztEQlLi88V1TBC2sMTKf8/ZIYqamCS2/2phA0mwCWhJNH7tYgaxRQRiJNb/u8kKUsQs cIhZ4vatKWBFwgK+En8nfGUEsVkEVCVetb5kAbF5BVwlXt29AbVNTuLmuU6wQZwCbhLfpq0D GsQBtM1V4uGnkAmMfAsYGVYxSqYWFOem5xYbFhjlpZbrFSfmFpfmpesl5+duYgSHtpbWDsY9 qz7oHWJk4mA8xCjBwawkwmtx7Eu8EG9KYmVValF+fFFpTmrxIUZpDhYlcd4LXSfjhQTSE0tS s1NTC1KLYLJMHJxSDUy+Z9fJMrttTqmf3bzGM/SjY0pd9ZrrHstW2znGMPUcSZQOcNqhoHb3 +zTN5RWBTX5+9UbTerVPXL22/OvLHwtFZp1L3/J3v57z9z1nz6m0z2A2ixTSsnOb0rPbQfrf qsKf23bnVZtfeP0reDqL0V22QrWc3S1pzVu690/fLbBo0bnazMmeK63UCz7p2PHKRB8oeuT/ S5WdebFBGcfBk5/WnErbybJ1m8Ka8soEj66j81V/Pdo7be8S1/SHDOFSO7+ta7hRyFpxssW1 SCv94JYVn3hsXqTHPT3+Xc7w+X+Hwx71Ex0ys6V23H/Zv754R1Jl5IkbTfJ3w/oyLJdYtkv0 1Qkoi/237s/eZSPq4q/EUpyRaKjFXFScCAB1M7GW3AIAAA== X-CMS-MailID: 20210107153030epcas5p14b0967c4d8d9804a2d084981af445c58 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20210107153030epcas5p14b0967c4d8d9804a2d084981af445c58 References: <1610033323-10560-1-git-send-email-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pankaj Dubey Many platforms use DesignWare controller but the PHY can be different in different platforms. If the PHY is compliant is to ZRX-DC specification it helps in low power consumption during power states. If current data rate is 8.0 GT/s or higher and PHY is not compliant to ZRX-DC specification, then after every 100ms link should transition to recovery state during the low power states. DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY. Platforms with ZRX-DC compliant PHY can set phy_zrxdc_compliant variable to specify this property to the controller. Signed-off-by: Anvesh Salveru Signed-off-by: Pankaj Dubey Signed-off-by: Shradha Todi Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Rob Herring Cc: Bjorn Helgaas --- drivers/pci/controller/dwc/pcie-designware.c | 6 ++++++ drivers/pci/controller/dwc/pcie-designware.h | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 645fa18..74590c7 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -722,4 +722,10 @@ void dw_pcie_setup(struct dw_pcie *pci) PCIE_PL_CHK_REG_CHK_REG_START; dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); } + + if (pci->phy_zrxdc_compliant) { + val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED); + val &= ~PORT_LOGIC_GEN3_ZRXDC_NONCOMPL; + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); + } } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 0207840..8b905a2 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -74,6 +74,9 @@ #define PCIE_MSI_INTR0_MASK 0x82C #define PCIE_MSI_INTR0_STATUS 0x830 +#define PCIE_PORT_GEN3_RELATED 0x890 +#define PORT_LOGIC_GEN3_ZRXDC_NONCOMPL BIT(0) + #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 #define PORT_MLTI_UPCFG_SUPPORT BIT(7) @@ -273,6 +276,7 @@ struct dw_pcie { u8 n_fts[2]; bool iatu_unroll_enabled: 1; bool io_cfg_atu_shared: 1; + bool phy_zrxdc_compliant; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)