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Thu, 7 Jan 2021 15:31:14 +0000 (GMT) From: Shradha Todi To: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org Cc: pankaj.dubey@samsung.com, sriram.dash@samsung.com, niyas.ahmed@samsung.com, p.rajanbabu@samsung.com, l.mehra@samsung.com, hari.tv@samsung.com, Shradha Todi , Rob Herring , Thierry Reding , Jonathan Hunter , Vidya Sagar Subject: [PATCH v7 5/5] arm64: tegra: Add support for ZRX DC PHY property Date: Thu, 7 Jan 2021 20:58:43 +0530 Message-Id: <1610033323-10560-6-git-send-email-shradha.t@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1610033323-10560-1-git-send-email-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpmleLIzCtJLcpLzFFi42LZdlhTU7fZ6Hu8wf/9ohYfp61ksmiZtYjF 4s7zG4wWl3fNYbM4O+84m0Xnl1lsFk+mPGK1OLox2GLR1i/sFq17j7Bb9B6utbixnt3i5655 LBbXtvM68HnsnHWX3WPTqk42j97md2wefVtWMXp83iQXwBrFZZOSmpNZllqkb5fAldH8bAZT wWeZivsX/7E0ME4W7WLk5JAQMJHYufIAYxcjF4eQwG5GiRmdE9ghnE+MErvPbWaFcL4xSsxe +hbI4QBrebPbECK+l1Gi891dFginhUniz/cbzCBz2QS0JBq/doHZIgJREjO3t4JNYha4yiSx e9Y2dpCEsICnxOup18CmsgioSiz/6wwS5hVwlXje28sOcZ+cxM1znWBzOAXcJL5NWwc2R0Lg J7vE2lu32SCKXCR6JuxkhrCFJV4d3wLVLCXx+d1eqJp8iakXnrJAfFAhsbynDiJsL3Hgyhyw MLOApsT6XfoQYVmJqafWMYHYzAJ8Er2/nzBBxHkldsyDsZUlvvzdwwJhS0rMO3aZFcL2kLj+ fw8zJExmMkrM2raGfQKj3CyEFQsYGVcxSqYWFOempxabFhjmpZbrFSfmFpfmpesl5+duYgSn Ey3PHYx3H3zQO8TIxMF4iFGCg1lJhNfi2Jd4Id6UxMqq1KL8+KLSnNTiQ4zSHCxK4rw7DB7E CwmkJ5akZqemFqQWwWSZODilGpg4vdiVHCfKGL2W17IufvKt+Vvr4aYTu++xvK91exwqtiV5 cvLV28VNT3W+Cuio2t0sCTH7pr5pY3hIb0mdvluJWP5W3qmsdi/8nRtWNgptNa5/trRc6GyE 9e75Oye1T9IN/iy1S231Tg6zXQ0pf/98nPavOrsxL1EiU81Jp7vnpLiuu2Bm6K4TdXMz3wjP v7vlpMv1XRwNm9csl/3MdGxB0K+Fj5K4LrNldtWf0LTt3cwR+TpyRfvWMus383fNtl5u4Cpr dHfq1Wj/mK/C5YW8AW+rhDPnJZdPVbs6IfYsY2f+3/Lwrc/npLk/c3qRZrJtcXNv1jY3z9J6 52BJnmDxYom/E3pDGSTua33drcRSnJFoqMVcVJwIAEVehaeWAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrMLMWRmVeSWpSXmKPExsWy7bCSvK6L5vd4g019whYfp61ksmiZtYjF 4s7zG4wWl3fNYbM4O+84m0Xnl1lsFk+mPGK1OLox2GLR1i/sFq17j7Bb9B6utbixnt3i5655 LBbXtvM68HnsnHWX3WPTqk42j97md2wefVtWMXp83iQXwBrFZZOSmpNZllqkb5fAldH8bAZT wWeZivsX/7E0ME4W7WLk4JAQMJF4s9uwi5GLQ0hgN6PEymuL2boYOYHikhKfL65jgrCFJVb+ e84OUdTEJLH77mlWkASbgJZE49cuZhBbRCBGYv2/m2BxZoGHTBKLN2qA2MICnhKvp15jBVnG IqAqsfyvM0iYV8BV4nlvLzvEfDmJm+c6wcZwCrhJfJu2DqxcCKjm4aeQCYx8CxgZVjFKphYU 56bnFhsWGOallusVJ+YWl+al6yXn525iBIerluYOxu2rPugdYmTiYDzEKMHBrCTCa3HsS7wQ b0piZVVqUX58UWlOavEhRmkOFiVx3gtdJ+OFBNITS1KzU1MLUotgskwcnFINTGa3YuZ/K66+ HrI9/dZLTkObJsGVxpuE+VbmVkX/becUuHI9QsndvzG/RWfZJK9PfTtyIrYpbjo4b0GK77lo 1SAmLvZpEqG9DJ+UJC7ZnJK3nlHj+3tK7s2iid37/XnsXzmx/9XYdf/vxU0tla+59be8nOJx i73JatK8VSy2W6f9Ug9J+beBKyV9fcbujk+S6zhuT/PryV90/Z2akJHulNVym/5vEbhivete 6sO9szlP3fTz2fdq7Z8n/26df9v26tpNsyiW7H3LatbnOalafSo//fUb6185h2N7N+ZJPtC4 uWLiOruObz8adt2S8HoSxpRiPn/O/6zLXeZHr0WyXtuY3P3h+Y1KnXYN042KnsFKLMUZiYZa zEXFiQBjRz7exgIAAA== X-CMS-MailID: 20210107153116epcas5p3510286e503e690537d5b2eb7486fa7ab X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20210107153116epcas5p3510286e503e690537d5b2eb7486fa7ab References: <1610033323-10560-1-git-send-email-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org DesignWare controller driver provides the support to handle the PHYs which are compliant to ZRX-DC specification based on "phy-zrxdc-compliant" DT property. So, add "phy-zrxdc-compliant" property in tegra PCIe PHY DT nodes. Signed-off-by: Pankaj Dubey Signed-off-by: Shradha Todi Cc: Rob Herring Cc: Thierry Reding Cc: Jonathan Hunter Cc: Vidya Sagar To: devicetree@vger.kernel.org To: linux-tegra@vger.kernel.org --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 25f36d6..9d91006 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1006,6 +1006,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_1: phy@3e20000 { @@ -1014,6 +1015,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_2: phy@3e30000 { @@ -1022,6 +1024,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_3: phy@3e40000 { @@ -1030,6 +1033,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_4: phy@3e50000 { @@ -1038,6 +1042,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_5: phy@3e60000 { @@ -1046,6 +1051,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_6: phy@3e70000 { @@ -1054,6 +1060,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_7: phy@3e80000 { @@ -1062,6 +1069,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_8: phy@3e90000 { @@ -1070,6 +1078,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_9: phy@3ea0000 { @@ -1078,6 +1087,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_nvhs_0: phy@3eb0000 { @@ -1086,6 +1096,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_nvhs_1: phy@3ec0000 { @@ -1094,6 +1105,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_nvhs_2: phy@3ed0000 { @@ -1102,6 +1114,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_nvhs_3: phy@3ee0000 { @@ -1110,6 +1123,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_nvhs_4: phy@3ef0000 { @@ -1118,6 +1132,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_nvhs_5: phy@3f00000 { @@ -1126,6 +1141,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_nvhs_6: phy@3f10000 { @@ -1134,6 +1150,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_nvhs_7: phy@3f20000 { @@ -1142,6 +1159,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_10: phy@3f30000 { @@ -1150,6 +1168,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_11: phy@3f40000 { @@ -1158,6 +1177,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; hsp_aon: hsp@c150000 {