| Message ID | 1616142247-13789-1-git-send-email-hongxing.zhu@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | [1/3] dt-bindings: imx6q-pcie: specify the imx8mq pcie phy voltage | expand |
Am Freitag, dem 19.03.2021 um 16:24 +0800 schrieb Richard Zhu: > Both 1.8v and 3.3v power supplies can be feeded to i.MX8MQ PCIe PHY. > In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data > sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, > the VREG_BYPASS bits of GPR registers should be cleared from default > value 1b'1 to 1b'0. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > --- > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > index de4b2baf91e8..23efbad9e804 100644 > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > @@ -59,6 +59,10 @@ Additional required properties for imx7d-pcie and imx8mq-pcie: > Additional required properties for imx8mq-pcie: > - clock-names: Must include the following additional entries: > - "pcie_aux" > +- pcie-vph-3v3: If present then PCIE_VPH is feeded by 3.3v in the HW > + schematic design. The PCIE_VPH is suggested to be 1.8v refer to the > + data sheet. If the PCIE_VPH is supplied by 3.3V, the VREG_BYPASS > + should be cleared to zero accordingly. Uhm, no. Please don't add boolean DT properties for random parts of the board design. If we need to know the voltage of PCIE_VPH, we should really add the VPH regulator as a supply to the PCIe controller node, then work out the voltage the usual way by using the Linux regulator API. Regards, Lucas
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index de4b2baf91e8..23efbad9e804 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -59,6 +59,10 @@ Additional required properties for imx7d-pcie and imx8mq-pcie: Additional required properties for imx8mq-pcie: - clock-names: Must include the following additional entries: - "pcie_aux" +- pcie-vph-3v3: If present then PCIE_VPH is feeded by 3.3v in the HW + schematic design. The PCIE_VPH is suggested to be 1.8v refer to the + data sheet. If the PCIE_VPH is supplied by 3.3V, the VREG_BYPASS + should be cleared to zero accordingly. Example:
Both 1.8v and 3.3v power supplies can be feeded to i.MX8MQ PCIe PHY. In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, the VREG_BYPASS bits of GPR registers should be cleared from default value 1b'1 to 1b'0. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 ++++ 1 file changed, 4 insertions(+)