From patchwork Fri Mar 19 08:24:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 12150393 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B38BC433DB for ; Fri, 19 Mar 2021 08:38:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E9EE164F1F for ; Fri, 19 Mar 2021 08:38:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234341AbhCSIh6 (ORCPT ); Fri, 19 Mar 2021 04:37:58 -0400 Received: from inva020.nxp.com ([92.121.34.13]:53970 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234390AbhCSIhi (ORCPT ); Fri, 19 Mar 2021 04:37:38 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E40FD1A535F; Fri, 19 Mar 2021 09:37:36 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 57F591A5358; Fri, 19 Mar 2021 09:37:30 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 695E24029D; Fri, 19 Mar 2021 09:37:22 +0100 (CET) From: Richard Zhu To: l.stach@pengutronix.de, andrew.smirnov@gmail.com, shawnguo@kernel.org, kw@linux.com, bhelgaas@google.com, stefan@agner.ch, lorenzo.pieralisi@arm.com Cc: linux-pci@vger.kernel.org, linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, Richard Zhu Subject: [PATCH 1/3] dt-bindings: imx6q-pcie: specify the imx8mq pcie phy voltage Date: Fri, 19 Mar 2021 16:24:05 +0800 Message-Id: <1616142247-13789-1-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Both 1.8v and 3.3v power supplies can be feeded to i.MX8MQ PCIe PHY. In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, the VREG_BYPASS bits of GPR registers should be cleared from default value 1b'1 to 1b'0. Signed-off-by: Richard Zhu --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index de4b2baf91e8..23efbad9e804 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -59,6 +59,10 @@ Additional required properties for imx7d-pcie and imx8mq-pcie: Additional required properties for imx8mq-pcie: - clock-names: Must include the following additional entries: - "pcie_aux" +- pcie-vph-3v3: If present then PCIE_VPH is feeded by 3.3v in the HW + schematic design. The PCIE_VPH is suggested to be 1.8v refer to the + data sheet. If the PCIE_VPH is supplied by 3.3V, the VREG_BYPASS + should be cleared to zero accordingly. Example: