From patchwork Sat Oct 9 16:44:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12547897 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A1FEC433EF for ; Sat, 9 Oct 2021 16:44:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2584360F4A for ; Sat, 9 Oct 2021 16:44:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232536AbhJIQqq (ORCPT ); Sat, 9 Oct 2021 12:46:46 -0400 Received: from mga09.intel.com ([134.134.136.24]:13426 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232176AbhJIQqn (ORCPT ); Sat, 9 Oct 2021 12:46:43 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10132"; a="226572038" X-IronPort-AV: E=Sophos;i="5.85,360,1624345200"; d="scan'208";a="226572038" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2021 09:44:45 -0700 X-IronPort-AV: E=Sophos;i="5.85,360,1624345200"; d="scan'208";a="479321217" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2021 09:44:45 -0700 Subject: [PATCH v3 09/10] cxl/pci: Use pci core's DVSEC functionality From: Dan Williams To: linux-cxl@vger.kernel.org Cc: Ben Widawsky , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, hch@lst.de Date: Sat, 09 Oct 2021 09:44:45 -0700 Message-ID: <163379788528.692348.11581080806976608802.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <163379783658.692348.16064992154261275220.stgit@dwillia2-desk3.amr.corp.intel.com> References: <163379783658.692348.16064992154261275220.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ben Widawsky Reduce maintenance burden of DVSEC query implementation by using the centralized PCI core implementation. Signed-off-by: Ben Widawsky [djbw: kill cxl_pci_dvsec()] Signed-off-by: Dan Williams Reviewed-by: Jonathan Cameron --- drivers/cxl/pci.c | 26 ++------------------------ 1 file changed, 2 insertions(+), 24 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index b6bc8e5ca028..f2e2a02d1fe6 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -340,29 +340,6 @@ static void cxl_unmap_regblock(struct pci_dev *pdev, map->base = NULL; } -static int cxl_pci_dvsec(struct pci_dev *pdev, int dvsec) -{ - int pos; - - pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DVSEC); - if (!pos) - return 0; - - while (pos) { - u16 vendor, id; - - pci_read_config_word(pdev, pos + PCI_DVSEC_HEADER1, &vendor); - pci_read_config_word(pdev, pos + PCI_DVSEC_HEADER2, &id); - if (vendor == PCI_DVSEC_VENDOR_ID_CXL && dvsec == id) - return pos; - - pos = pci_find_next_ext_capability(pdev, pos, - PCI_EXT_CAP_ID_DVSEC); - } - - return 0; -} - static int cxl_probe_regs(struct pci_dev *pdev, struct cxl_register_map *map) { struct cxl_component_reg_map *comp_map; @@ -449,7 +426,8 @@ static int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, u32 regloc_size, regblocks; int regloc, i; - regloc = cxl_pci_dvsec(pdev, PCI_DVSEC_ID_CXL_REGLOC_DVSEC_ID); + regloc = pci_find_dvsec_capability(pdev, PCI_DVSEC_VENDOR_ID_CXL, + PCI_DVSEC_ID_CXL_REGLOC_DVSEC_ID); if (!regloc) return -ENXIO;