From patchwork Sat Oct 9 16:44:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12547899 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A54AC433EF for ; Sat, 9 Oct 2021 16:44:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 055F160F4A for ; Sat, 9 Oct 2021 16:44:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232477AbhJIQqv (ORCPT ); Sat, 9 Oct 2021 12:46:51 -0400 Received: from mga02.intel.com ([134.134.136.20]:6955 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232387AbhJIQqt (ORCPT ); Sat, 9 Oct 2021 12:46:49 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10132"; a="213816794" X-IronPort-AV: E=Sophos;i="5.85,360,1624345200"; d="scan'208";a="213816794" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2021 09:44:51 -0700 X-IronPort-AV: E=Sophos;i="5.85,360,1624345200"; d="scan'208";a="546557593" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2021 09:44:51 -0700 Subject: [PATCH v3 10/10] ocxl: Use pci core's DVSEC functionality From: Dan Williams To: linux-cxl@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, Andrew Donnellan , Frederic Barrat , Ben Widawsky , Andrew Donnellan , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, hch@lst.de Date: Sat, 09 Oct 2021 09:44:50 -0700 Message-ID: <163379789065.692348.7117946955275586530.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <163379783658.692348.16064992154261275220.stgit@dwillia2-desk3.amr.corp.intel.com> References: <163379783658.692348.16064992154261275220.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ben Widawsky Reduce maintenance burden of DVSEC query implementation by using the centralized PCI core implementation. There are two obvious places to simply drop in the new core implementation. There remains find_dvsec_from_pos() which would benefit from using a core implementation. As that change is less trivial it is reserved for later. Cc: linuxppc-dev@lists.ozlabs.org Cc: Andrew Donnellan Acked-by: Frederic Barrat (v1) Signed-off-by: Ben Widawsky Reviewed-by: Andrew Donnellan Signed-off-by: Dan Williams --- arch/powerpc/platforms/powernv/ocxl.c | 3 ++- drivers/misc/ocxl/config.c | 13 +------------ 2 files changed, 3 insertions(+), 13 deletions(-) diff --git a/arch/powerpc/platforms/powernv/ocxl.c b/arch/powerpc/platforms/powernv/ocxl.c index 9105efcf242a..28b009b46464 100644 --- a/arch/powerpc/platforms/powernv/ocxl.c +++ b/arch/powerpc/platforms/powernv/ocxl.c @@ -107,7 +107,8 @@ static int get_max_afu_index(struct pci_dev *dev, int *afu_idx) int pos; u32 val; - pos = find_dvsec_from_pos(dev, OCXL_DVSEC_FUNC_ID, 0); + pos = pci_find_dvsec_capability(dev, PCI_VENDOR_ID_IBM, + OCXL_DVSEC_FUNC_ID); if (!pos) return -ESRCH; diff --git a/drivers/misc/ocxl/config.c b/drivers/misc/ocxl/config.c index a68738f38252..e401a51596b9 100644 --- a/drivers/misc/ocxl/config.c +++ b/drivers/misc/ocxl/config.c @@ -33,18 +33,7 @@ static int find_dvsec(struct pci_dev *dev, int dvsec_id) { - int vsec = 0; - u16 vendor, id; - - while ((vsec = pci_find_next_ext_capability(dev, vsec, - OCXL_EXT_CAP_ID_DVSEC))) { - pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET, - &vendor); - pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id); - if (vendor == PCI_VENDOR_ID_IBM && id == dvsec_id) - return vsec; - } - return 0; + return pci_find_dvsec_capability(dev, PCI_VENDOR_ID_IBM, dvsec_id); } static int find_dvsec_afu_ctrl(struct pci_dev *dev, u8 afu_idx)