| Message ID | 1644303749-4610-1-git-send-email-hongxing.zhu@nxp.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | arm64: dts: imx8mq-evk: Add the second pcie port support | expand |
In subject:
s/Add the/Add/
s/pcie/PCIe/
On Tue, Feb 08, 2022 at 03:02:29PM +0800, Richard Zhu wrote:
> Enable the secone PCIe port support on i.MX8MQ EVK board.
s/secone/second/
> -----Original Message----- > From: Bjorn Helgaas <helgaas@kernel.org> > Sent: 2022年2月8日 23:29 > To: Hongxing Zhu <hongxing.zhu@nxp.com> > Cc: shawnguo@kernel.org; l.stach@pengutronix.de; linux-pci@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com> > Subject: Re: [PATCH] arm64: dts: imx8mq-evk: Add the second pcie port > support > > In subject: > > s/Add the/Add/ > s/pcie/PCIe/ > > On Tue, Feb 08, 2022 at 03:02:29PM +0800, Richard Zhu wrote: > > Enable the secone PCIe port support on i.MX8MQ EVK board. > > s/secone/second/ Thanks a lot for your quickly review. Would be changed a moment later. Best Regards Richard
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index a1b7582f3ecf..06f6e44da4d4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -27,6 +27,17 @@ pcie0_refclk: pcie0-refclk { clock-frequency = <100000000>; }; + reg_pcie1: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-vsd-3v3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_usdhc2>; @@ -327,6 +338,20 @@ &pcie0 { status = "okay"; }; +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + vpcie-supply = <®_pcie1>; + vph-supply = <&vgen5_reg>; + status = "okay"; +}; + &pgc_gpu { power-supply = <&sw1a_reg>; }; @@ -482,6 +507,19 @@ MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 >; }; + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + >; + }; + + pinctrl_pcie1_reg: pcie1reggrp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 + >; + }; + pinctrl_qspi: qspigrp { fsl,pins = < MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
Enable the secone PCIe port support on i.MX8MQ EVK board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 38 ++++++++++++++++++++ 1 file changed, 38 insertions(+)