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Mon, 15 Jul 2024 18:13:53 GMT Received: from hu-mrana-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 15 Jul 2024 11:13:53 -0700 From: Mayank Rana To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , Mayank Rana Subject: [PATCH V226/7] dt-bindings: PCI: host-generic-pci: Add snps,dw-pcie-ecam-msi binding Date: Mon, 15 Jul 2024 11:13:34 -0700 Message-ID: <1721067215-5832-7-git-send-email-quic_mrana@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1721067215-5832-1-git-send-email-quic_mrana@quicinc.com> References: <1721067215-5832-1-git-send-email-quic_mrana@quicinc.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: T4gnOBKDQXQBRBiziBzzidh6lptryqV2 X-Proofpoint-GUID: T4gnOBKDQXQBRBiziBzzidh6lptryqV2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-15_12,2024-07-11_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 bulkscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 spamscore=0 phishscore=0 mlxlogscore=972 mlxscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407150142 To support MSI functionality using Synopsys DesignWare PCIe controller based MSI controller with ECAM driver, add "snps,dw-pcie-ecam-msi compatible binding which uses provided SPIs to support MSI functionality. Signed-off-by: Mayank Rana --- .../devicetree/bindings/pci/host-generic-pci.yaml | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml index 9c714fa..9e860d5 100644 --- a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml @@ -81,6 +81,12 @@ properties: - marvell,armada8k-pcie-ecam - socionext,synquacer-pcie-ecam - const: snps,dw-pcie-ecam + - description: | + Firmware is configuring Synopsys DesignWare PCIe controller in RC mode with + ECAM compatible fashion. To use MSI controller of Synopsys DesignWare PCIe + controller for MSI functionality, this compatible is used. + items: + - const: snps,dw-pcie-ecam-msi - description: CAM or ECAM compliant PCI host controllers without any quirks enum: @@ -116,6 +122,20 @@ properties: A phandle to the node that controls power or/and system resource or interface to firmware to enable ECAM compliant PCIe root complex. + interrupts: + description: + DWC PCIe Root Port/Complex specific MSI interrupt/IRQs. + minItems: 1 + maxItems: 8 + + interrupt-names: + description: + MSI interrupt names + minItems: 1 + maxItems: 8 + items: + pattern: '^msi[0-9]+$' + required: - compatible - reg @@ -146,11 +166,22 @@ allOf: reg: maxItems: 1 + - if: + properties: + compatible: + contains: + const: snps,dw-pcie-ecam-msi + then: + required: + - interrupts + - interrupt-names + unevaluatedProperties: false examples: - | + #include bus { #address-cells = <2>; #size-cells = <2>; @@ -180,5 +211,31 @@ examples: interrupt-map-mask = <0xf800 0x0 0x0 0x7>; power-domains = <&scmi5_pd 0>; }; + + pcie0: pci@1c00000 { + compatible = "snps,dw-pcie-ecam-msi"; + reg = <0x4 0x00000000 0 0x10000000>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>, + <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x40000000>; + bus-range = <0x00 0xff>; + dma-coherent; + linux,pci-domain = <0>; + power-domains = <&scmi5_pd 0>; + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7"; + }; }; ...