From patchwork Thu Sep 26 06:07:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 13812827 X-Patchwork-Delegate: manivannanece23@gmail.com Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8ACE5187FF9; Thu, 26 Sep 2024 06:30:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727332231; cv=none; b=ffcdmPwgX7icGntV6vbSQ3FGONr3dzd+RVYWSL5V+AOwdzuEFuA222x/WyekZD+e9svuJx8rRP4/ZOTe8b32lLUmyMabrT8RIBpwoy+iVewwYJT+ubZbgz15IPXlp5PismV+/WXtdKuDHVpRFDLfqWno6W4qfSIevaMRH8Xy0OY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727332231; c=relaxed/simple; bh=afvAKIHmWPRVCIw7juwXjk4oeFecKkCmQ+VPiaqDARA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=m19n8UkwDElH9PCcJ3HeUhFPKgGOVEHuL7MKcKHIvYW0UMGnc6OvPn/XxT9sUehr7hn1vevG0hMhO6h27hl07qcbFMd3qPTn/vWAvNY65lPM+Bysft3LG5EQ1z0l31r+n6lzPU5BP6Qwc9lomUNqtFKvHleE4HmnwsvMUio01PE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 1F0CE1A18F3; Thu, 26 Sep 2024 08:30:28 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E278F1A0367; Thu, 26 Sep 2024 08:30:27 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 9E41D183F0C2; Thu, 26 Sep 2024 14:30:24 +0800 (+08) From: Richard Zhu To: l.stach@pengutronix.de, kwilczynski@kernel.org, bhelgaas@google.com, lpieralisi@kernel.org, frank.li@nxp.com, robh+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, krzysztof.kozlowski+dt@linaro.org, festevam@gmail.com, s.hauer@pengutronix.de Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev, Richard Zhu Subject: [PATCH v3 2/9] PCI: imx6: Add ref clock for i.MX95 PCIe Date: Thu, 26 Sep 2024 14:07:46 +0800 Message-Id: <1727330873-17486-3-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1727330873-17486-1-git-send-email-hongxing.zhu@nxp.com> References: <1727330873-17486-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add "ref" clock to enable reference clock. If use external clock, ref clock should point to external reference. If use internal clock, CREF_EN in LAST_TO_REG controls reference output, which implement in drivers/clk/imx/clk-imx95-blk-ctl.c. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 0dbc333adcff..2aa02674c817 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1480,6 +1480,7 @@ static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"}; static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}; static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"}; static const char * const imx8q_clks[] = {"mstr", "slv", "dbi"}; +static const char * const imx95_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux", "ref"}; static const struct imx_pcie_drvdata drvdata[] = { [IMX6Q] = { @@ -1593,8 +1594,8 @@ static const struct imx_pcie_drvdata drvdata[] = { [IMX95] = { .variant = IMX95, .flags = IMX_PCIE_FLAG_HAS_SERDES, - .clk_names = imx8mq_clks, - .clks_cnt = ARRAY_SIZE(imx8mq_clks), + .clk_names = imx95_clks, + .clks_cnt = ARRAY_SIZE(imx95_clks), .ltssm_off = IMX95_PE0_GEN_CTRL_3, .ltssm_mask = IMX95_PCIE_LTSSM_EN, .mode_off[0] = IMX95_PE0_GEN_CTRL_1,