@@ -583,3 +583,17 @@ Description:
enclosure-specific indications "specific0" to "specific7",
hence the corresponding led class devices are unavailable if
the DSM interface is used.
+
+What: /sys/bus/pci/devices/.../p2p_link/links
+Date: September 2024
+Contact: Shivasharan S <shivasharan.srikanteshwara@broadcom.com>
+Description:
+ This file appears on PCIe upstream ports which supports an
+ internal P2P link.
+ Reading this attribute will provide the list of other upstream
+ ports on the system which have an internal P2P link available
+ between the two ports.
+Users:
+ Userspace applications interested in determining a optimal P2P
+ link for data transfers between devices connected to the PCIe
+ switches.
@@ -155,3 +155,12 @@ config PCIE_EDR
the PCI Firmware Specification r3.2. Enable this if you want to
support hybrid DPC model which uses both firmware and OS to
implement DPC.
+
+config PCIE_P2P_LINK
+ bool "PCI Express P2P link detection support"
+ depends on PCIEPORTBUS
+ help
+ This option enables the PCIe port driver to export sysfs entries
+ for Inter switch P2P links detected on the PCIe upstream ports.
+ This option enables user space libraries to detect optimal paths
+ for data transfers between endpoints connected to PCIe switches.
@@ -13,3 +13,4 @@ obj-$(CONFIG_PCIE_PME) += pme.o
obj-$(CONFIG_PCIE_DPC) += dpc.o
obj-$(CONFIG_PCIE_PTM) += ptm.o
obj-$(CONFIG_PCIE_EDR) += edr.o
+obj-$(CONFIG_PCIE_P2P_LINK) += p2p_link.o
new file mode 100644
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Purpose: PCI Express P2P link discovery
+ *
+ * Copyright (C) 2024 Broadcom Inc.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/pci.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/bitops.h>
+
+#include "../pci.h"
+#include "portdrv.h"
+#include "p2p_link.h"
+
+/**
+ * pcie_brcm_is_p2p_supported - Broadcom device specific handler
+ * to check if the upstream port supports inter switch P2P.
+ *
+ * @dev: PCIe upstream port to check
+ *
+ * This function assumes the PCIe upstream port is a Broadcom
+ * PCIe device.
+ */
+static bool pcie_brcm_is_p2p_supported(struct pci_dev *dev)
+{
+ u64 dsn;
+ u16 vsec;
+ u32 vsec_data;
+
+ vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_LSI_LOGIC,
+ PCIE_BRCM_SW_P2P_VSEC_ID);
+ if (!vsec) {
+ pci_dbg(dev, "Failed to get VSEC capability\n");
+ return false;
+ }
+
+ pci_read_config_dword(dev, vsec + PCIE_BRCM_SW_P2P_MODE_VSEC_OFFSET,
+ &vsec_data);
+
+ dsn = pci_get_dsn(dev);
+ if (!dsn) {
+ pci_dbg(dev, "DSN capability is not present\n");
+ return false;
+ }
+
+ pci_dbg(dev, "Serial Number: 0x%llx VSEC 0x%x\n",
+ dsn, vsec_data);
+
+ /* Check if the PEX switch has a valid P2P support */
+ if (!(dsn & PCIE_BRCM_SW_DSN_P2P_STATUS))
+ return false;
+
+ return FIELD_GET(PCIE_BRCM_SW_P2P_MODE_MASK, vsec_data) ==
+ PCIE_BRCM_SW_P2P_MODE_INTER_SW_LINK;
+}
+
+/*
+ * Determine if device supports Inter switch P2P links.
+ *
+ * Return value: true if inter switch P2P is supported, return false otherwise.
+ */
+static bool pcie_port_is_p2p_supported(struct pci_dev *dev)
+{
+ /* P2P link attribute is supported on upstream ports only */
+ if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
+ return false;
+
+ /*
+ * Currently Broadcom PEX switches are supported.
+ */
+ if (dev->vendor == PCI_VENDOR_ID_LSI_LOGIC &&
+ (dev->device == PCI_DEVICE_ID_BRCM_PEX_89000_HLC ||
+ dev->device == PCI_DEVICE_ID_BRCM_PEX_89000_LLC))
+ return pcie_brcm_is_p2p_supported(dev);
+
+ return false;
+}
+
+/*
+ * Traverse list of all PCI bridges and find devices that support Inter switch P2P
+ * and have the same serial number to create report the BDF over sysfs.
+ */
+static ssize_t links_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct pci_dev *pdev = to_pci_dev(dev), *pdev_link = NULL;
+ size_t len = 0;
+ u64 dsn, dsn_link;
+
+ /*
+ * pdev's DSN has already been verified to be available before creating
+ * the sysfs entry.
+ */
+ dsn = pci_get_dsn(pdev);
+
+ /* Traverse list of PCI bridges to determine any available P2P links */
+ while ((pdev_link = pci_get_class(PCI_CLASS_BRIDGE_PCI << 8, pdev_link))
+ != NULL) {
+ if (pdev_link == pdev)
+ continue;
+
+ if (!pcie_port_is_p2p_supported(pdev_link))
+ continue;
+
+ dsn_link = pci_get_dsn(pdev_link);
+ if (!dsn_link)
+ continue;
+
+ if (dsn == dsn_link)
+ len += sysfs_emit_at(buf, len, "%04x:%02x:%02x.%d\n",
+ pci_domain_nr(pdev_link->bus),
+ pdev_link->bus->number, PCI_SLOT(pdev_link->devfn),
+ PCI_FUNC(pdev_link->devfn));
+ }
+
+ return len;
+}
+
+/* P2P link sysfs attribute. */
+static struct device_attribute dev_attr_links =
+ __ATTR(links, 0444, links_show, NULL);
+
+static struct attribute *pcie_port_p2p_link_attrs[] = {
+ &dev_attr_links.attr,
+ NULL
+};
+
+const struct attribute_group pcie_port_p2p_link_attr_group = {
+ .name = "p2p_link",
+ .attrs = pcie_port_p2p_link_attrs,
+};
+
+void p2p_link_sysfs_update_group(struct pci_dev *pdev)
+{
+ if (!pcie_port_is_p2p_supported(pdev))
+ return;
+
+ sysfs_update_group(&pdev->dev.kobj, &pcie_port_p2p_link_attr_group);
+}
new file mode 100644
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Purpose: PCI Express P2P link discovery
+ *
+ * Copyright (C) 2024 Broadcom Inc.
+ */
+
+#ifndef _P2P_LINK_H_
+#define _P2P_LINK_H_
+
+/* P2P Link supported device IDs */
+#define PCI_DEVICE_ID_BRCM_PEX_89000_HLC 0xC030
+#define PCI_DEVICE_ID_BRCM_PEX_89000_LLC 0xC034
+
+#define PCIE_BRCM_SW_P2P_VSEC_ID 0x1
+#define PCIE_BRCM_SW_P2P_MODE_VSEC_OFFSET 0xC
+#define PCIE_BRCM_SW_P2P_MODE_MASK GENMASK(9, 8)
+#define PCIE_BRCM_SW_P2P_MODE_INTER_SW_LINK 0x2
+#define PCIE_BRCM_SW_DSN_P2P_STATUS BIT(3)
+
+#ifdef CONFIG_PCIE_P2P_LINK
+void p2p_link_sysfs_update_group(struct pci_dev *pdev);
+
+#else
+static inline void p2p_link_sysfs_update_group(struct pci_dev *pdev) { }
+#endif
+#endif /* _P2P_LINK_H_ */
@@ -21,6 +21,7 @@
#include "../pci.h"
#include "portdrv.h"
+#include "p2p_link.h"
/*
* The PCIe Capability Interrupt Message Number (PCIe r3.1, sec 7.8.2) must
@@ -714,7 +715,9 @@ static int pcie_portdrv_probe(struct pci_dev *dev,
pm_runtime_put_autosuspend(&dev->dev);
pm_runtime_allow(&dev->dev);
}
-
+#ifdef CONFIG_PCIE_P2P_LINK
+ p2p_link_sysfs_update_group(dev);
+#endif
return 0;
}
Broadcom PCI switches supports inter-switch P2P links between two PCI-to-PCI bridges. This presents an optimal data path for data movement. The patch exports a new sysfs entry for PCI devices that support the inter switch P2P links and reports the B:D:F information of the devices that are connected through this inter switch link as shown below: Host root bridge --------------------------------------- | | NIC1 --- PCI Switch1 --- Inter-switch link --- PCI Switch2 --- NIC2 (2c:00.0) (2a:00.0) (3d:00.0) (40:00.0) | | GPU1 GPU2 (2d:00.0) (3f:00.0) SERVER 1 $ find /sys/ -name "links" | xargs grep . /sys/devices/pci0000:29/0000:29:01.0/0000:2a:00.0/p2p_link/links:0000:3d:00.0 /sys/devices/pci0000:3c/0000:3c:01.0/0000:3d:00.0/p2p_link/links:0000:2a:00.0 Current support is added to report the P2P links available for Broadcom switches based on the capability that is reported by the upstream bridges through their vendor-specific capability registers. Signed-off-by: Shivasharan S <shivasharan.srikanteshwara@broadcom.com> Signed-off-by: Sumanesh Samanta <sumanesh.samanta@broadcom.com> --- Changes in v3: Moved the link detection code to separate file that can be enabled with config option CONFIG_PCIE_P2P_LINK Changes in v2: Integrated the code into PCIe portdrv to create the sysfs entries during probe, as suggested by Mani. Documentation/ABI/testing/sysfs-bus-pci | 14 +++ drivers/pci/pcie/Kconfig | 9 ++ drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/p2p_link.c | 143 ++++++++++++++++++++++++ drivers/pci/pcie/p2p_link.h | 27 +++++ drivers/pci/pcie/portdrv.c | 5 +- 6 files changed, 198 insertions(+), 1 deletion(-) create mode 100644 drivers/pci/pcie/p2p_link.c create mode 100644 drivers/pci/pcie/p2p_link.h