From patchwork Wed Jun 10 19:56:31 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Morton X-Patchwork-Id: 29391 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n5AJvd4q003381 for ; Wed, 10 Jun 2009 19:57:45 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761608AbZFJT4h (ORCPT ); Wed, 10 Jun 2009 15:56:37 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1761611AbZFJT4h (ORCPT ); Wed, 10 Jun 2009 15:56:37 -0400 Received: from smtp1.linux-foundation.org ([140.211.169.13]:47835 "EHLO smtp1.linux-foundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1761609AbZFJT4f (ORCPT ); Wed, 10 Jun 2009 15:56:35 -0400 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id n5AJuV5L031396 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 10 Jun 2009 12:56:32 -0700 Received: from localhost.localdomain (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with ESMTP id n5AJuV5Y009506; Wed, 10 Jun 2009 12:56:31 -0700 Message-Id: <200906101956.n5AJuV5Y009506@imap1.linux-foundation.org> Subject: [patch 2/4] pci-quirks: unhide 'Overflow' device on i828{6, 7}5P/PE chipsets To: jbarnes@virtuousgeek.org Cc: linux-pci@vger.kernel.org, akpm@linux-foundation.org, mirq-linux@rere.qmqm.pl, norsk5@yahoo.com From: akpm@linux-foundation.org Date: Wed, 10 Jun 2009 12:56:31 -0700 X-Spam-Status: No, hits=-3.502 required=5 tests=AWL, BAYES_00, OSDL_HEADER_SUBJECT_BRACKETED X-Spam-Checker-Version: SpamAssassin 3.2.4-osdl_revision__1.47__ X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Michal Miroslaw Some BIOSes hide 'overflow' device (dev #6) for i82875P/PE chipsets. The same happens for i82865P/PE. Add a quirk to enable this device. This allows i82875 EDAC driver to bind to chipset's dev #6 and not dev #0 as the latter is used by AGP driver. On my laptop (i82865P based) ACPI code is disabling this device again in \_SB.PCI0._CRS method (called at least at PNP init time). This can be easily worked around by patching DSDT. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: Michal Miroslaw Cc: Jesse Barnes Acked-by: Doug Thompson Signed-off-by: Andrew Morton --- drivers/pci/quirks.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff -puN drivers/pci/quirks.c~pci-quirks-unhide-overflow-device-on-i828675p-pe-chipsets-v2 drivers/pci/quirks.c --- a/drivers/pci/quirks.c~pci-quirks-unhide-overflow-device-on-i828675p-pe-chipsets-v2 +++ a/drivers/pci/quirks.c @@ -2017,6 +2017,28 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BR PCI_DEVICE_ID_NX2_5709S, quirk_brcm_570x_limit_vpd); +/* Originally in EDAC sources for i82875P: + * Intel tells BIOS developers to hide device 6 which + * configures the overflow device access containing + * the DRBs - this is where we expose device 6. + * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm + */ +static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev) +{ + u8 reg; + + if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { + dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); + pci_write_config_byte(dev, 0xF4, reg | 0x02); + } +} + +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, + quirk_unhide_mch_dev6); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, + quirk_unhide_mch_dev6); + + #ifdef CONFIG_PCI_MSI /* Some chipsets do not support MSI. We cannot easily rely on setting * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually