From patchwork Wed Dec 5 20:57:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 1843061 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id B0A0C40B17 for ; Wed, 5 Dec 2012 20:57:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964816Ab2LEU5s (ORCPT ); Wed, 5 Dec 2012 15:57:48 -0500 Received: from mail-gh0-f202.google.com ([209.85.160.202]:35002 "EHLO mail-gh0-f202.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754260Ab2LEU5r (ORCPT ); Wed, 5 Dec 2012 15:57:47 -0500 Received: by mail-gh0-f202.google.com with SMTP id z10so671231ghb.1 for ; Wed, 05 Dec 2012 12:57:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; bh=7dxxKb7kjbqbsItCkcj0Wq/RuibkVJIYUFwe+dONcKA=; b=Kv1Wi//2POs1hTDa6vAlo+iapohq4hBwdDXt9tEcn1wvmBToXERXppnGP02GMyQKXj x9wNHw34bhSjWYG8A6Sqih29zqt5xxnO3MZQE8H1EHsyHYVsOEX6FaS75rmit6qsBcNw F91KtCKhir4jqB/26SizlR4tIcJEKIyDtbEog3kVqGN54k9v3YFegds1LNMVxa7O+EoY Cjxx5iGcyr4R2DJxlhdqblhxe7WSEv9HbIgcJEDdyja2XqQBt0v2b/MZpOc3zgrFtF/n /vkwfq9t2FWP+f5b/E8CZ4nfjbT1WrUweOHapi2ydD87fW/iZAEwobkMKLZtTBbDPWiJ 9Gkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding :x-gm-message-state; bh=7dxxKb7kjbqbsItCkcj0Wq/RuibkVJIYUFwe+dONcKA=; b=WswhWSx9Y9t6KuceYDIRajMuliKVdXHtNqdMdHCs/ZZhWOPiu1sN9/Hc2Og5IK7qjK cqyL01ZOsLWBC9RkHbE2DVxzLISKn4Or/7DmnQQpnnqIHVRrkuEh2mVsQ63q6A1BGfcE C0z/OfZMVE7VOp2hff9dXzmS6Y5kA8yOXBR5GR3471xmRwKHp+lC6lQfGP6zEF9WIMNo /KOzTmBnxQOrj0MAs8yXeNxx73AEJiZy/P8q+DR4WsZlCG5EA6AZZ7Gpv9ZMJQk76nSb ynPJoCESosWhbm6x6LWeUw5fIUmPGKP2yCQjGpUWZzofqzZsaV9Cn1oashCq5w5Zr5Np cxDQ== Received: by 10.236.173.201 with SMTP id v49mr11823277yhl.19.1354741066220; Wed, 05 Dec 2012 12:57:46 -0800 (PST) Received: from wpzn3.hot.corp.google.com (216-239-44-65.google.com [216.239.44.65]) by gmr-mx.google.com with ESMTPS id i27si475011yhb.0.2012.12.05.12.57.46 (version=TLSv1/SSLv3 cipher=AES128-SHA); Wed, 05 Dec 2012 12:57:46 -0800 (PST) Received: from bhelgaas.mtv.corp.google.com (bhelgaas.mtv.corp.google.com [172.17.131.112]) by wpzn3.hot.corp.google.com (Postfix) with ESMTP id 0EE05100047; Wed, 5 Dec 2012 12:57:46 -0800 (PST) Received: from bhelgaas.mtv.corp.google.com (unknown [IPv6:::1]) by bhelgaas.mtv.corp.google.com (Postfix) with ESMTP id BE1D2180280; Wed, 5 Dec 2012 12:57:45 -0800 (PST) Subject: [PATCH 05/12] PCI: Add standard PCIe Capability Link ASPM field names To: linux-pci@vger.kernel.org From: Bjorn Helgaas Cc: Shaohua Li , Kenji Kaneshige Date: Wed, 05 Dec 2012 13:57:45 -0700 Message-ID: <20121205205745.13851.5032.stgit@bhelgaas.mtv.corp.google.com> In-Reply-To: <20121205205724.13851.50508.stgit@bhelgaas.mtv.corp.google.com> References: <20121205205724.13851.50508.stgit@bhelgaas.mtv.corp.google.com> User-Agent: StGit/0.15 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQkpLAFh/G9Uvb9n5Yftsw516ucsEDLCAtQ+D+0148zEYuUjH8LdaxrQJtfpbudlAUbBeDEPdy896zDKOl9BdLhb+nkW5ReSGCzsKbuHFvQmBaWh2ryxPmwYegObsKBVBqx3dTX8LqmGC0s1HCt7Cm8to5OyDYvcZbHyx23V9InBn1zk6uUkp4CcGWx7/7bpJRZxwQKTxNbDSTONWQrKx6E0ZQ23DQ== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add standard #defines for ASPM fields in PCI Express Link Capability and Link Control registers. Previously we used PCIE_LINK_STATE_L0S and PCIE_LINK_STATE_L1 directly, but these are defined for the Linux ASPM interfaces, e.g., pci_disable_link_state(), and only coincidentally match the actual register bits. PCIE_LINK_STATE_CLKPM, also part of that interface, does not match the register bit. Signed-off-by: Bjorn Helgaas CC: Kenji Kaneshige CC: Shaohua Li --- drivers/pci/pcie/aspm.c | 11 ++++++----- include/uapi/linux/pci_regs.h | 2 ++ 2 files changed, 8 insertions(+), 5 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 213753b..c2faf9d 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -427,7 +427,8 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) { - pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, 0x3, val); + pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_ASPMC, val); } static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) @@ -442,12 +443,12 @@ static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) return; /* Convert ASPM state to upstream/downstream ASPM register state */ if (state & ASPM_STATE_L0S_UP) - dwstream |= PCIE_LINK_STATE_L0S; + dwstream |= PCI_EXP_LNKCTL_ASPM_L0S; if (state & ASPM_STATE_L0S_DW) - upstream |= PCIE_LINK_STATE_L0S; + upstream |= PCI_EXP_LNKCTL_ASPM_L0S; if (state & ASPM_STATE_L1) { - upstream |= PCIE_LINK_STATE_L1; - dwstream |= PCIE_LINK_STATE_L1; + upstream |= PCI_EXP_LNKCTL_ASPM_L1; + dwstream |= PCI_EXP_LNKCTL_ASPM_L1; } /* * Spec 2.0 suggests all functions should be configured the diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 4cca834..0b6dbe4 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -469,6 +469,8 @@ #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ #define PCI_EXP_LNKCTL 16 /* Link Control */ #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ +#define PCI_EXP_LNKCTL_ASPM_L0S 0x01 /* L0s Enable */ +#define PCI_EXP_LNKCTL_ASPM_L1 0x02 /* L1 Enable */ #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ #define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */ #define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */