From patchwork Fri Oct 11 02:13:02 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 3020351 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CB2C69F243 for ; Fri, 11 Oct 2013 02:13:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EA6712025B for ; Fri, 11 Oct 2013 02:13:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0BE92202FF for ; Fri, 11 Oct 2013 02:13:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752264Ab3JKCNI (ORCPT ); Thu, 10 Oct 2013 22:13:08 -0400 Received: from mail-out.m-online.net ([212.18.0.10]:34997 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752233Ab3JKCNH (ORCPT ); Thu, 10 Oct 2013 22:13:07 -0400 Received: from frontend1.mail.m-online.net (frontend1.mail.intern.m-online.net [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 3cwt3y6pQsz3hhVb; Fri, 11 Oct 2013 04:13:02 +0200 (CEST) X-Auth-Info: OKwihYc0rkuFaa8lr0g9L3cGNyFLSsrh5do58fCReww= Received: from chi.localnet (unknown [195.140.253.167]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp-auth.mnet-online.de (Postfix) with ESMTPSA id 3cwt3y5WWgzbbpJ; Fri, 11 Oct 2013 04:13:02 +0200 (CEST) From: Marek Vasut To: Bjorn Helgaas Subject: Re: [PATCH v7 0/2] Add PCIe support for i.MX6q Date: Fri, 11 Oct 2013 04:13:02 +0200 User-Agent: KMail/1.13.7 (Linux/3.10-2-amd64; KDE/4.10.5; x86_64; ; ) Cc: "Zhu Richard-R65037" , "linux-arm-kernel@lists.infradead.org" , Shawn Guo , "linux-pci@vger.kernel.org" , "tharvey@gateworks.com" , Frank Li , Sean Cross , Sascha Hauer , Yinghai Lu , Tim Harvey References: <1380165887-13506-1-git-send-email-shawn.guo@linaro.org> <201310101939.44295.marex@denx.de> In-Reply-To: MIME-Version: 1.0 Message-Id: <201310110413.02354.marex@denx.de> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Bjorn, > On Thu, Oct 10, 2013 at 11:39 AM, Marek Vasut wrote: > > Hi Bjorn, > > > >> [+cc Yinghai] > >> > >> On Thu, Oct 10, 2013 at 9:58 AM, Marek Vasut wrote: > >> >> On Thu, Oct 10, 2013 at 4:25 AM, Marek Vasut wrote: > >> > I tried you suggestion, this is what I got now (and with V7 of the > >> > patches): > >> > > >> > Note that my topology is: rootport->2_port_switch->ethernet_chip , the > >> > other port of the switch is not used . > >> > > >> > imx6q-pcie 1ffc000.pcie: phy link never came up After discussing with Tim a little, looks like a clock bit was missing. The above line was the cause of all the issues. Now I can probe the bus, but I still need more patches: This dirty patch here limits the PCIe operation to GEN1 only. It's based on this Freescale patch [1]. Without this change, the PCIe switch is not detected. Any idea why? (I also had to increase the PHY startup delay to get GEN1 going). [1] https://www.osadl.org/monitoring/patches/r8s7/1342-ENGR00180230-MX6-PCIE- enlarge-the-eye-diagram-and-fo.patch Best regards, Marek Vasut --- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 32b30ca..df2838b 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -330,13 +330,16 @@ static void imx6_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); +// Enable GEN1 +writel(((readl(pp->dbi_base + 0x7c) & 0xfffffff0) | 0x1), pp->dbi_base + 0x7c); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); while (!dw_pcie_link_up(pp)) { usleep_range(100, 1000); count++; - if (count >= 10) { + if (count >= 200) { dev_err(pp->dev, "phy link never came up\n"); dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",