From patchwork Thu Feb 13 03:03:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 3642031 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7ECA9BF13A for ; Thu, 13 Feb 2014 03:04:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C0BB320165 for ; Thu, 13 Feb 2014 03:04:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DC08B20158 for ; Thu, 13 Feb 2014 03:04:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752638AbaBMDCX (ORCPT ); Wed, 12 Feb 2014 22:02:23 -0500 Received: from mail-pa0-f44.google.com ([209.85.220.44]:41332 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752619AbaBMDCT (ORCPT ); Wed, 12 Feb 2014 22:02:19 -0500 Received: by mail-pa0-f44.google.com with SMTP id kq14so10120536pab.31 for ; Wed, 12 Feb 2014 19:02:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=SU0DTf/lNQsUVwN4/ahqNDNnVKoQiv75WphbTEh6XHg=; b=oD6St36W0Ugty2aL/xO6Ry/bvs6RwTgRw+0rsZUInv1lyuq6hwMyupiBiq5MyWfytg wHwBqvcKvB6PoCgFROkOXxCLwhEYcorz5dzgbtf0gzGmQ1NvL7ATHvH4I52tAiFUz/Sn +peQOd9PNldO4G6qmcrn5k26gQd0pszKMf27wOeJrpS35peOVKP0E2Eyt5qAym0HtCE/ YqRVdFNKsB/QEMdngD84eDC2yluArEfQEBc+sxEH/G2PispVxhTyz/dUZThx537dDift UwDsK957gsKdfA2LfdmsSQ+4UAvfxwnPtiiX36RBlUoxTyPJPZbfqVWeIQ4W/YPtsL72 lROA== X-Received: by 10.68.196.164 with SMTP id in4mr55056249pbc.128.1392260539226; Wed, 12 Feb 2014 19:02:19 -0800 (PST) Received: from [127.0.0.1] (s214090.ppp.asahi-net.or.jp. [220.157.214.90]) by mx.google.com with ESMTPSA id qs1sm1020806pbb.18.2014.02.12.19.02.15 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 12 Feb 2014 19:02:17 -0800 (PST) From: Magnus Damm To: linux-pci@vger.kernel.org Cc: horms@verge.net.au, linux-sh@vger.kernel.org, linux-kernel@vger.kernel.org, valentine.barshak@cogentembedded.com, ben.dooks@codethink.co.uk, geert@linux-m68k.org, bhelgaas@google.com, Magnus Damm Date: Thu, 13 Feb 2014 12:03:32 +0900 Message-Id: <20140213030332.10398.67426.sendpatchset@w520> In-Reply-To: <20140213030302.10398.37322.sendpatchset@w520> References: <20140213030302.10398.37322.sendpatchset@w520> Subject: [PATCH 03/08] PCI: rcar: fix bridge logic configuration accesses Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Dooks The bridge logic at slot 0 only supports reads up to 0x40 and the rest of the PCI configuration space for this slot is marked as reserved in the manual. Trying a read from offset 0x100 is producing an error from the bridge. With error interrupts enabled, the following is printed: pci-rcar-gen2 ee0d0000.pci: error irq: status 00000014 Signed-off-by: Ben Dooks Signed-off-by: Magnus Damm --- drivers/pci/host/pci-rcar-gen2.c | 4 ++++ 1 file changed, 4 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- 0005/drivers/pci/host/pci-rcar-gen2.c +++ work/drivers/pci/host/pci-rcar-gen2.c 2014-02-13 09:45:45.000000000 +0900 @@ -119,6 +119,10 @@ static void __iomem *rcar_pci_cfg_base(s if (slot > 2) return NULL; + /* bridge logic only has registers to 0x40 */ + if (slot == 0x0 && where >= 0x40) + return NULL; + val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG : RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;