Message ID | 20151022153455.GA16360@localhost (mailing list archive) |
---|---|
State | New, archived |
Delegated to: | Bjorn Helgaas |
Headers | show |
On Thu, Oct 22, 2015 at 9:04 PM, Bjorn Helgaas <helgaas@kernel.org> wrote: > On Thu, Oct 22, 2015 at 11:04:26AM +0200, Lucas Stach wrote: >> I'm not sure if I like the removal of all the LTSSM state defines, as >> not all reference manuals include them and so I liked to have the header >> as a reference. But if you prefer to not carry unused defines in the >> kernel I won't object strongly to the removal. >> >> Otherwise the series looks fine, which you may take as a Reviewed-by. > > Thanks, Lucas. > > OK, I put the rest of the LTSSM #defines back in > drivers/pci/host/pcie-designware.h as a separate patch (below): > Thanks for putting it back. Its useful to debug issues related to link training, which one finds many a time with new silicon. And as Lucas pointed, its not mentioned in most of the user manual. I remember, I had to grep it into RTL code :(. For the series Acked-by: Pratyush Anand <pratyush.anand@gmail.com> -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index efe5fca..8cb5725 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -22,8 +22,39 @@ #define MAX_MSI_IRQS 32 #define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32) +#define LTSSM_STATE_DETECT_QUIET 0x00 +#define LTSSM_STATE_DETECT_ACT 0x01 +#define LTSSM_STATE_POLL_ACTIVE 0x02 +#define LTSSM_STATE_POLL_COMPLIANCE 0x03 +#define LTSSM_STATE_POLL_CONFIG 0x04 +#define LTSSM_STATE_PRE_DETECT_QUIET 0x05 +#define LTSSM_STATE_DETECT_WAIT 0x06 +#define LTSSM_STATE_CFG_LINKWD_START 0x07 +#define LTSSM_STATE_CFG_LINKWD_ACCEPT 0x08 +#define LTSSM_STATE_CFG_LANENUM_WAIT 0x09 +#define LTSSM_STATE_CFG_LANENUM_ACCEPT 0x0a +#define LTSSM_STATE_CFG_COMPLETE 0x0b +#define LTSSM_STATE_CFG_IDLE 0x0c #define LTSSM_STATE_RCVRY_LOCK 0x0d +#define LTSSM_STATE_RCVRY_SPEED 0x0e +#define LTSSM_STATE_RCVRY_RCVRCFG 0x0f +#define LTSSM_STATE_RCVRY_IDLE 0x10 #define LTSSM_STATE_L0 0x11 +#define LTSSM_STATE_L0S 0x12 +#define LTSSM_STATE_L123_SEND_EIDLE 0x13 +#define LTSSM_STATE_L1_IDLE 0x14 +#define LTSSM_STATE_L2_IDLE 0x15 +#define LTSSM_STATE_L2_WAKE 0x16 +#define LTSSM_STATE_DISABLED_ENTRY 0x17 +#define LTSSM_STATE_DISABLED_IDLE 0x18 +#define LTSSM_STATE_DISABLED 0x19 +#define LTSSM_STATE_LPBK_ENTRY 0x1a +#define LTSSM_STATE_LPBK_ACTIVE 0x1b +#define LTSSM_STATE_LPBK_EXIT 0x1c +#define LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1d +#define LTSSM_STATE_HOT_RESET_ENTRY 0x1e +#define LTSSM_STATE_HOT_RESET 0x1f + #define LTSSM_STATE_MASK 0x1f struct pcie_port {