From patchwork Sat Jun 11 19:10:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 9171119 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4D8ED60865 for ; Sat, 11 Jun 2016 19:10:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 36ADB2654B for ; Sat, 11 Jun 2016 19:10:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1E7C520410; Sat, 11 Jun 2016 19:10:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B2D6F24B44 for ; Sat, 11 Jun 2016 19:10:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752236AbcFKTKj (ORCPT ); Sat, 11 Jun 2016 15:10:39 -0400 Received: from mail.kernel.org ([198.145.29.136]:50290 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751823AbcFKTKi (ORCPT ); Sat, 11 Jun 2016 15:10:38 -0400 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 585702013D; Sat, 11 Jun 2016 19:10:36 +0000 (UTC) Received: from localhost (unknown [64.22.252.3]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4FE172013A; Sat, 11 Jun 2016 19:10:35 +0000 (UTC) Date: Sat, 11 Jun 2016 14:10:33 -0500 From: Bjorn Helgaas To: Niklas Cassel Cc: niklass@axis.com, jespern@axis.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux-arm-kernel@axis.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/2] dt-bindings: pci: add DT binding for Axis ARTPEC-6 PCIe controller Message-ID: <20160611191033.GL16462@localhost> References: <1462794507-30262-1-git-send-email-niklass@axis.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1462794507-30262-1-git-send-email-niklass@axis.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Mon, May 09, 2016 at 01:48:27PM +0200, Niklas Cassel wrote: > From: Niklas Cassel > > This commit adds the Device Tree binding documentation that allows to > describe the PCIe controller found in the Axis ARTPEC-6 SoC. > > Signed-off-by: Niklas Cassel I applied both of these, with Rob's ack on the first, to pci/host-artpec for v4.8, thanks! I made the following minor edits; hopefully I didn't break anything: --- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt index f91b916..330a45b 100644 --- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt +++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt @@ -1,11 +1,11 @@ * Axis ARTPEC-6 PCIe interface -This PCIe host controller is based on the Synopsys Designware PCIe IP +This PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in designware-pcie.txt. Required properties: - compatible: "axis,artpec6-pcie", "snps,dw-pcie" -- reg: base addresses and lengths of the pcie controller (DBI), +- reg: base addresses and lengths of the PCIe controller (DBI), the phy controller, and configuration address space. - reg-names: Must include the following entries: - "dbi" diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index 1a2de8f..033d9ad 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -250,5 +250,8 @@ config PCIE_ARTPEC6 depends on MACH_ARTPEC6 select PCIE_DW select PCIEPORTBUS + help + Say Y here to enable PCIe controller support on Axis ARTPEC-6 + SoCs. This PCIe controller uses the DesignWare core. endmenu diff --git a/drivers/pci/host/pcie-artpec6.c b/drivers/pci/host/pcie-artpec6.c index d53dbaf..19adc77 100644 --- a/drivers/pci/host/pcie-artpec6.c +++ b/drivers/pci/host/pcie-artpec6.c @@ -61,7 +61,7 @@ struct artpec6_pcie { #define PHY_STATUS 0x118 #define PHY_COSPLLLOCK (1 << 0) -#define ARTPEC6_CPU_TO_BUS_ADDR 0x0FFFFFFF +#define ARTPEC6_CPU_TO_BUS_ADDR 0x0fffffff static int artpec6_pcie_establish_link(struct pcie_port *pp) { @@ -241,35 +241,26 @@ static int __init artpec6_pcie_probe(struct platform_device *pdev) dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base); - if (IS_ERR(pp->dbi_base)) { - ret = PTR_ERR(pp->dbi_base); - goto fail; - } + if (IS_ERR(pp->dbi_base)) + return PTR_ERR(pp->dbi_base); phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); artpec6_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base); - if (IS_ERR(artpec6_pcie->phy_base)) { - ret = PTR_ERR(artpec6_pcie->phy_base); - goto fail; - } + if (IS_ERR(artpec6_pcie->phy_base)) + return PTR_ERR(artpec6_pcie->phy_base); artpec6_pcie->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "axis,syscon-pcie"); - if (IS_ERR(artpec6_pcie->regmap)) { - ret = PTR_ERR(artpec6_pcie->regmap); - goto fail; - } + if (IS_ERR(artpec6_pcie->regmap)) + return PTR_ERR(artpec6_pcie->regmap); ret = artpec6_add_pcie_port(pp, pdev); if (ret < 0) - goto fail; + return ret; platform_set_drvdata(pdev, artpec6_pcie); return 0; - -fail: - return ret; } static const struct of_device_id artpec6_pcie_of_match[] = {