From patchwork Fri Sep 16 20:02:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yinghai Lu X-Patchwork-Id: 9336565 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5FBA36089F for ; Fri, 16 Sep 2016 20:03:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4F7852A091 for ; Fri, 16 Sep 2016 20:03:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 444752A097; Fri, 16 Sep 2016 20:03:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 85D1F2A091 for ; Fri, 16 Sep 2016 20:03:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965341AbcIPUDC (ORCPT ); Fri, 16 Sep 2016 16:03:02 -0400 Received: from userp1040.oracle.com ([156.151.31.81]:23989 "EHLO userp1040.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965324AbcIPUC5 (ORCPT ); Fri, 16 Sep 2016 16:02:57 -0400 Received: from userv0021.oracle.com (userv0021.oracle.com [156.151.31.71]) by userp1040.oracle.com (Sentrion-MTA-4.3.2/Sentrion-MTA-4.3.2) with ESMTP id u8GK2b2N022162 (version=TLSv1 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 16 Sep 2016 20:02:37 GMT Received: from aserv0121.oracle.com (aserv0121.oracle.com [141.146.126.235]) by userv0021.oracle.com (8.13.8/8.13.8) with ESMTP id u8GK2aT4024731 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 16 Sep 2016 20:02:37 GMT Received: from abhmp0011.oracle.com (abhmp0011.oracle.com [141.146.116.17]) by aserv0121.oracle.com (8.13.8/8.13.8) with ESMTP id u8GK2aJa008397; Fri, 16 Sep 2016 20:02:36 GMT Received: from aserv0021.oracle.com (/10.132.126.127) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Fri, 16 Sep 2016 13:02:36 -0700 From: Yinghai Lu To: Bjorn Helgaas , David Miller , Benjamin Herrenschmidt Cc: Wei Yang , Khalid Aziz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Yinghai Lu Subject: [PATCH v14 17/17] PCI: Restore pref MMIO allocation logic for host bridge without mmio64 Date: Fri, 16 Sep 2016 13:02:07 -0700 Message-Id: <20160916200207.21439-18-yinghai@kernel.org> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160916200207.21439-1-yinghai@kernel.org> References: <20160916200207.21439-1-yinghai@kernel.org> X-Source-IP: userv0021.oracle.com [156.151.31.71] Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From 5b2854155 (PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources), we change the logic for pref mmio allocation: When bridge pref support mmio64, we will only put children pref that support mmio64 into it, and will put children pref mmio32 into bridge's non-pref mmio32. That could leave bridge pref bar not used when that pref bar is mmio64, and children res only has mmio32. Also could have allocation failure when non-pref mmio32 is not big enough space for those children pref mmio32. That is not rational when the host bridge does not have 64bit mmio above 4g at all. The patch restore to old logic: when host bridge does not have has_mem64, put children pref mmio64 and pref mmio32 all under bridges pref bars. Signed-off-by: Yinghai Lu Tested-by: Khalid Aziz --- drivers/pci/bus.c | 4 +++- drivers/pci/setup-bus.c | 13 +++++++++---- drivers/pci/setup-res.c | 9 ++++++--- 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c index c288e5a..33a56a4 100644 --- a/drivers/pci/bus.c +++ b/drivers/pci/bus.c @@ -233,8 +233,10 @@ int pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res, { #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT int rc; + unsigned long mmio64 = pci_find_host_bridge(bus)->has_mem64 ? + IORESOURCE_MEM_64 : 0; - if (res->flags & IORESOURCE_MEM_64) { + if (res->flags & mmio64) { rc = pci_bus_alloc_from_region(bus, res, size, align, min, type_mask, alignf, alignf_data, &pci_high); diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 1fcfa13..89d8c88 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1316,7 +1316,8 @@ void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head) b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES]; mask = IORESOURCE_MEM; prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; - if (b_res[2].flags & IORESOURCE_MEM_64) { + if ((b_res[2].flags & IORESOURCE_MEM_64) && + pci_find_host_bridge(bus)->has_mem64) { prefmask |= IORESOURCE_MEM_64; ret = pbus_size_mem(bus, prefmask, prefmask, prefmask, prefmask, @@ -1586,17 +1587,21 @@ static void pci_bridge_release_resources(struct pci_bus *bus, * io port. * 2. if there is non pref mmio assign fail, release bridge * nonpref mmio. - * 3. if there is 64bit pref mmio assign fail, and bridge pref + * 3. if there is pref mmio assign fail, and host bridge does + * have 64bit mmio, release bridge pref mmio. + * 4. if there is 64bit pref mmio assign fail, and bridge pref * is 64bit, release bridge pref mmio. - * 4. if there is pref mmio assign fail, and bridge pref is + * 5. if there is pref mmio assign fail, and bridge pref is * 32bit mmio, release bridge pref mmio - * 5. if there is pref mmio assign fail, and bridge pref is not + * 6. if there is pref mmio assign fail, and bridge pref is not * assigned, release bridge nonpref mmio. */ if (type & IORESOURCE_IO) idx = 0; else if (!(type & IORESOURCE_PREFETCH)) idx = 1; + else if (!pci_find_host_bridge(bus)->has_mem64) + idx = 2; else if ((type & IORESOURCE_MEM_64) && (b_res[2].flags & IORESOURCE_MEM_64)) idx = 2; diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index f741fed..59271ee 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -212,6 +212,8 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, struct resource *res = dev->resource + resno; resource_size_t min; int ret; + unsigned long mmio64 = pci_find_host_bridge(bus)->has_mem64 ? + IORESOURCE_MEM_64 : 0; min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; @@ -223,7 +225,7 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, * things differently than they were sized, not everything will fit. */ ret = pci_bus_alloc_resource(bus, res, size, align, min, - IORESOURCE_PREFETCH | IORESOURCE_MEM_64, + IORESOURCE_PREFETCH | mmio64, pcibios_align_resource, dev); if (ret == 0) return 0; @@ -232,7 +234,8 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, * If the prefetchable window is only 32 bits wide, we can put * 64-bit prefetchable resources in it. */ - if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) == + if (mmio64 && + (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) == (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) { ret = pci_bus_alloc_resource(bus, res, size, align, min, IORESOURCE_PREFETCH, @@ -247,7 +250,7 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, * non-prefetchable, the first call already tried the only possibility * so we don't need to try again. */ - if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) + if (res->flags & (IORESOURCE_PREFETCH | mmio64)) ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, pcibios_align_resource, dev);