From patchwork Fri Oct 7 16:29:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 9366683 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1629060487 for ; Fri, 7 Oct 2016 16:29:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 077CC29776 for ; Fri, 7 Oct 2016 16:29:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F078929778; Fri, 7 Oct 2016 16:29:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9382E29776 for ; Fri, 7 Oct 2016 16:29:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S938813AbcJGQ32 (ORCPT ); Fri, 7 Oct 2016 12:29:28 -0400 Received: from mail.kernel.org ([198.145.29.136]:49030 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936336AbcJGQ3V (ORCPT ); Fri, 7 Oct 2016 12:29:21 -0400 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AC509203EC; Fri, 7 Oct 2016 16:29:06 +0000 (UTC) Received: from localhost (unknown [69.55.156.165]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 944942011D; Fri, 7 Oct 2016 16:29:05 +0000 (UTC) Subject: [PATCH 3/9] PCI: xilinx: Swap order of xilinx_writel() reg/val arguments To: Michal Simek , =?utf-8?b?U8O2cmVu?= Brinkmann From: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Date: Fri, 07 Oct 2016 11:29:03 -0500 Message-ID: <20161007162903.24137.66452.stgit@bhelgaas-glaptop2.roam.corp.google.com> In-Reply-To: <20161007162847.24137.38713.stgit@bhelgaas-glaptop2.roam.corp.google.com> References: <20161007162847.24137.38713.stgit@bhelgaas-glaptop2.roam.corp.google.com> User-Agent: StGit/0.16 MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Swap order of xilinx_writel() arguments to match the "dev, pos, val" order used by pci_write_config_word() and other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pcie-xilinx.c | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index f8e4c22..b840737 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -123,7 +123,8 @@ static inline u32 xilinx_readl(struct xilinx_pcie_port *xilinx, u32 reg) return readl(xilinx->reg_base + reg); } -static inline void xilinx_writel(struct xilinx_pcie_port *xilinx, u32 val, u32 reg) +static inline void xilinx_writel(struct xilinx_pcie_port *xilinx, u32 reg, + u32 val) { writel(val, xilinx->reg_base + reg); } @@ -145,8 +146,8 @@ static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *xilinx) if (val & XILINX_PCIE_RPEFR_ERR_VALID) { dev_dbg(xilinx->dev, "Requester ID %lu\n", val & XILINX_PCIE_RPEFR_REQ_ID); - xilinx_writel(xilinx, XILINX_PCIE_RPEFR_ALL_MASK, - XILINX_PCIE_REG_RPEFR); + xilinx_writel(xilinx, XILINX_PCIE_REG_RPEFR, + XILINX_PCIE_RPEFR_ALL_MASK); } } @@ -343,8 +344,8 @@ static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *xilinx) xilinx->msi_pages = __get_free_pages(GFP_KERNEL, 0); msg_addr = virt_to_phys((void *)xilinx->msi_pages); - xilinx_writel(xilinx, 0x0, XILINX_PCIE_REG_MSIBASE1); - xilinx_writel(xilinx, msg_addr, XILINX_PCIE_REG_MSIBASE2); + xilinx_writel(xilinx, XILINX_PCIE_REG_MSIBASE1, 0); + xilinx_writel(xilinx, XILINX_PCIE_REG_MSIBASE2, msg_addr); } /* INTx Functions */ @@ -435,8 +436,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) { /* Clear interrupt FIFO register 1 */ - xilinx_writel(xilinx, XILINX_PCIE_RPIFR1_ALL_MASK, - XILINX_PCIE_REG_RPIFR1); + xilinx_writel(xilinx, XILINX_PCIE_REG_RPIFR1, + XILINX_PCIE_RPIFR1_ALL_MASK); /* Handle INTx Interrupt */ val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >> @@ -460,8 +461,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) XILINX_PCIE_RPIFR2_MSG_DATA; /* Clear interrupt FIFO register 1 */ - xilinx_writel(xilinx, XILINX_PCIE_RPIFR1_ALL_MASK, - XILINX_PCIE_REG_RPIFR1); + xilinx_writel(xilinx, XILINX_PCIE_REG_RPIFR1, + XILINX_PCIE_RPIFR1_ALL_MASK); if (IS_ENABLED(CONFIG_PCI_MSI)) { /* Handle MSI Interrupt */ @@ -499,8 +500,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) error: /* Clear the Interrupt Decode register */ - xilinx_writel(xilinx, status, XILINX_PCIE_REG_IDR); - + xilinx_writel(xilinx, XILINX_PCIE_REG_IDR, status); return IRQ_HANDLED; } @@ -560,21 +560,20 @@ static void xilinx_pcie_init_port(struct xilinx_pcie_port *xilinx) dev_info(xilinx->dev, "PCIe Link is DOWN\n"); /* Disable all interrupts */ - xilinx_writel(xilinx, ~XILINX_PCIE_IDR_ALL_MASK, - XILINX_PCIE_REG_IMR); + xilinx_writel(xilinx, XILINX_PCIE_REG_IMR, ~XILINX_PCIE_IDR_ALL_MASK); /* Clear pending interrupts */ - xilinx_writel(xilinx, xilinx_readl(xilinx, XILINX_PCIE_REG_IDR) & - XILINX_PCIE_IMR_ALL_MASK, - XILINX_PCIE_REG_IDR); + xilinx_writel(xilinx, XILINX_PCIE_REG_IDR, + xilinx_readl(xilinx, XILINX_PCIE_REG_IDR) & + XILINX_PCIE_IMR_ALL_MASK); /* Enable all interrupts */ - xilinx_writel(xilinx, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR); + xilinx_writel(xilinx, XILINX_PCIE_REG_IMR, XILINX_PCIE_IMR_ALL_MASK); /* Enable the Bridge enable bit */ - xilinx_writel(xilinx, xilinx_readl(xilinx, XILINX_PCIE_REG_RPSC) | - XILINX_PCIE_REG_RPSC_BEN, - XILINX_PCIE_REG_RPSC); + xilinx_writel(xilinx, XILINX_PCIE_REG_RPSC, + xilinx_readl(xilinx, XILINX_PCIE_REG_RPSC) | + XILINX_PCIE_REG_RPSC_BEN); } /**