From patchwork Fri Oct 7 16:30:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 9366697 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 95A5460487 for ; Fri, 7 Oct 2016 16:30:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8730E29776 for ; Fri, 7 Oct 2016 16:30:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7C2A929778; Fri, 7 Oct 2016 16:30:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1B5FD29776 for ; Fri, 7 Oct 2016 16:30:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756096AbcJGQaW (ORCPT ); Fri, 7 Oct 2016 12:30:22 -0400 Received: from mail.kernel.org ([198.145.29.136]:49596 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753234AbcJGQaV (ORCPT ); Fri, 7 Oct 2016 12:30:21 -0400 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3934620260; Fri, 7 Oct 2016 16:30:20 +0000 (UTC) Received: from localhost (unknown [69.55.156.165]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 244242011D; Fri, 7 Oct 2016 16:30:19 +0000 (UTC) Subject: [PATCH 2/7] PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces To: Joao Pinto , Pratyush Anand From: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Date: Fri, 07 Oct 2016 11:30:17 -0500 Message-ID: <20161007163017.24388.75972.stgit@bhelgaas-glaptop2.roam.corp.google.com> In-Reply-To: <20161007163009.24388.11253.stgit@bhelgaas-glaptop2.roam.corp.google.com> References: <20161007163009.24388.11253.stgit@bhelgaas-glaptop2.roam.corp.google.com> User-Agent: StGit/0.16 MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The struct pcie_host_ops.readl_rc() and .writel_rc() function pointers allow a driver to override the default DesignWare register accessors. Make the signature of the override functions the same as the default accessors. This makes the default dw_pcie_readl_rc() and the corresponding override more structurally similar: both will compute the final register address with "pp->dbi_base + reg". Previously dw_pcie_readl_rc() computed the address and passed it to the override. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pci-exynos.c | 10 ++++------ drivers/pci/host/pcie-designware.c | 4 ++-- drivers/pci/host/pcie-designware.h | 5 ++--- 3 files changed, 8 insertions(+), 11 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index 2e2d7f0..b29e9d6 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -425,22 +425,20 @@ static void exynos_pcie_enable_interrupts(struct pcie_port *pp) exynos_pcie_msi_init(pp); } -static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp, - void __iomem *dbi_base) +static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg) { u32 val; exynos_pcie_sideband_dbi_r_mode(pp, true); - val = readl(dbi_base); + val = readl(pp->dbi_base + reg); exynos_pcie_sideband_dbi_r_mode(pp, false); return val; } -static inline void exynos_pcie_writel_rc(struct pcie_port *pp, - u32 val, void __iomem *dbi_base) +static inline void exynos_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) { exynos_pcie_sideband_dbi_w_mode(pp, true); - writel(val, dbi_base); + writel(val, pp->dbi_base + reg); exynos_pcie_sideband_dbi_w_mode(pp, false); } diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index b58f078..c5b54a3 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -144,7 +144,7 @@ int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val) static inline u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg) { if (pp->ops->readl_rc) - return pp->ops->readl_rc(pp, pp->dbi_base + reg); + return pp->ops->readl_rc(pp, reg); return readl(pp->dbi_base + reg); } @@ -152,7 +152,7 @@ static inline u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg) static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) { if (pp->ops->writel_rc) - pp->ops->writel_rc(pp, val, pp->dbi_base + reg); + pp->ops->writel_rc(pp, val, reg); else writel(val, pp->dbi_base + reg); } diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index c8e5bc6..60cbc68 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -54,9 +54,8 @@ struct pcie_port { }; struct pcie_host_ops { - u32 (*readl_rc)(struct pcie_port *pp, void __iomem *dbi_base); - void (*writel_rc)(struct pcie_port *pp, - u32 val, void __iomem *dbi_base); + u32 (*readl_rc)(struct pcie_port *pp, u32 reg); + void (*writel_rc)(struct pcie_port *pp, u32 val, u32 reg); int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,