From patchwork Fri Oct 7 16:35:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 9366797 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CBD6360D00 for ; Fri, 7 Oct 2016 16:36:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BD9FF29777 for ; Fri, 7 Oct 2016 16:36:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B229129773; Fri, 7 Oct 2016 16:36:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6A7212977E for ; Fri, 7 Oct 2016 16:36:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S940551AbcJGQgD (ORCPT ); Fri, 7 Oct 2016 12:36:03 -0400 Received: from mail.kernel.org ([198.145.29.136]:54262 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757322AbcJGQf7 (ORCPT ); Fri, 7 Oct 2016 12:35:59 -0400 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 75E9020340; Fri, 7 Oct 2016 16:35:58 +0000 (UTC) Received: from localhost (unknown [69.55.156.165]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id DA3262013D; Fri, 7 Oct 2016 16:35:55 +0000 (UTC) Subject: [PATCH 4/8] PCI: exynos: Reorder accessor functions To: Jingoo Han , Krzysztof Kozlowski , Kukjin Kim From: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org Date: Fri, 07 Oct 2016 11:35:54 -0500 Message-ID: <20161007163554.25314.62435.stgit@bhelgaas-glaptop2.roam.corp.google.com> In-Reply-To: <20161007163526.25314.29033.stgit@bhelgaas-glaptop2.roam.corp.google.com> References: <20161007163526.25314.29033.stgit@bhelgaas-glaptop2.roam.corp.google.com> User-Agent: StGit/0.16 MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Reorder the accessors so the reader is first, as most other drivers do. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pci-exynos.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index c7b0809..5f54ab5 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -102,19 +102,14 @@ struct exynos_pcie { #define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7) #define PCIE_PHY_TRSV3_LVCC 0x31c -static void exynos_elb_writel(struct exynos_pcie *exynos, u32 val, u32 reg) -{ - writel(val, exynos->elbi_base + reg); -} - static u32 exynos_elb_readl(struct exynos_pcie *exynos, u32 reg) { return readl(exynos->elbi_base + reg); } -static void exynos_phy_writel(struct exynos_pcie *exynos, u32 val, u32 reg) +static void exynos_elb_writel(struct exynos_pcie *exynos, u32 val, u32 reg) { - writel(val, exynos->phy_base + reg); + writel(val, exynos->elbi_base + reg); } static u32 exynos_phy_readl(struct exynos_pcie *exynos, u32 reg) @@ -122,9 +117,9 @@ static u32 exynos_phy_readl(struct exynos_pcie *exynos, u32 reg) return readl(exynos->phy_base + reg); } -static void exynos_blk_writel(struct exynos_pcie *exynos, u32 val, u32 reg) +static void exynos_phy_writel(struct exynos_pcie *exynos, u32 val, u32 reg) { - writel(val, exynos->block_base + reg); + writel(val, exynos->phy_base + reg); } static u32 exynos_blk_readl(struct exynos_pcie *exynos, u32 reg) @@ -132,6 +127,11 @@ static u32 exynos_blk_readl(struct exynos_pcie *exynos, u32 reg) return readl(exynos->block_base + reg); } +static void exynos_blk_writel(struct exynos_pcie *exynos, u32 val, u32 reg) +{ + writel(val, exynos->block_base + reg); +} + static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *exynos, bool on) { u32 val;