From patchwork Fri Oct 7 16:36:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 9366807 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0800C608A6 for ; Fri, 7 Oct 2016 16:36:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ED71229773 for ; Fri, 7 Oct 2016 16:36:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E21D029779; Fri, 7 Oct 2016 16:36:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 81FB629777 for ; Fri, 7 Oct 2016 16:36:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S941091AbcJGQgJ (ORCPT ); Fri, 7 Oct 2016 12:36:09 -0400 Received: from mail.kernel.org ([198.145.29.136]:54426 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S941022AbcJGQgI (ORCPT ); Fri, 7 Oct 2016 12:36:08 -0400 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C3DC920340; Fri, 7 Oct 2016 16:36:06 +0000 (UTC) Received: from localhost (unknown [69.55.156.165]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 3913F2013D; Fri, 7 Oct 2016 16:36:05 +0000 (UTC) Subject: [PATCH 5/8] PCI: exynos: Swap order of exynos_elb_writel() reg/val arguments To: Jingoo Han , Krzysztof Kozlowski , Kukjin Kim From: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org Date: Fri, 07 Oct 2016 11:36:03 -0500 Message-ID: <20161007163603.25314.16022.stgit@bhelgaas-glaptop2.roam.corp.google.com> In-Reply-To: <20161007163526.25314.29033.stgit@bhelgaas-glaptop2.roam.corp.google.com> References: <20161007163526.25314.29033.stgit@bhelgaas-glaptop2.roam.corp.google.com> User-Agent: StGit/0.16 MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Swap order of exynos_elb_writel() arguments to match the "dev, pos, val" order used by pci_write_config_word() and other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pci-exynos.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index 5f54ab5..eb50b1a 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -107,7 +107,7 @@ static u32 exynos_elb_readl(struct exynos_pcie *exynos, u32 reg) return readl(exynos->elbi_base + reg); } -static void exynos_elb_writel(struct exynos_pcie *exynos, u32 val, u32 reg) +static void exynos_elb_writel(struct exynos_pcie *exynos, u32 reg, u32 val) { writel(val, exynos->elbi_base + reg); } @@ -139,11 +139,11 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *exynos, bool on) if (on) { val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_AWMISC); val |= PCIE_ELBI_SLV_DBI_ENABLE; - exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_AWMISC); + exynos_elb_writel(exynos, PCIE_ELBI_SLV_AWMISC, val); } else { val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_AWMISC); val &= ~PCIE_ELBI_SLV_DBI_ENABLE; - exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_AWMISC); + exynos_elb_writel(exynos, PCIE_ELBI_SLV_AWMISC, val); } } @@ -154,11 +154,11 @@ static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *exynos, bool on) if (on) { val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_ARMISC); val |= PCIE_ELBI_SLV_DBI_ENABLE; - exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_ARMISC); + exynos_elb_writel(exynos, PCIE_ELBI_SLV_ARMISC, val); } else { val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_ARMISC); val &= ~PCIE_ELBI_SLV_DBI_ENABLE; - exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_ARMISC); + exynos_elb_writel(exynos, PCIE_ELBI_SLV_ARMISC, val); } } @@ -168,10 +168,10 @@ static void exynos_pcie_assert_core_reset(struct exynos_pcie *exynos) val = exynos_elb_readl(exynos, PCIE_CORE_RESET); val &= ~PCIE_CORE_RESET_ENABLE; - exynos_elb_writel(exynos, val, PCIE_CORE_RESET); - exynos_elb_writel(exynos, 0, PCIE_PWR_RESET); - exynos_elb_writel(exynos, 0, PCIE_STICKY_RESET); - exynos_elb_writel(exynos, 0, PCIE_NONSTICKY_RESET); + exynos_elb_writel(exynos, PCIE_CORE_RESET, val); + exynos_elb_writel(exynos, PCIE_PWR_RESET, 0); + exynos_elb_writel(exynos, PCIE_STICKY_RESET, 0); + exynos_elb_writel(exynos, PCIE_NONSTICKY_RESET, 0); } static void exynos_pcie_deassert_core_reset(struct exynos_pcie *exynos) @@ -181,11 +181,11 @@ static void exynos_pcie_deassert_core_reset(struct exynos_pcie *exynos) val = exynos_elb_readl(exynos, PCIE_CORE_RESET); val |= PCIE_CORE_RESET_ENABLE; - exynos_elb_writel(exynos, val, PCIE_CORE_RESET); - exynos_elb_writel(exynos, 1, PCIE_STICKY_RESET); - exynos_elb_writel(exynos, 1, PCIE_NONSTICKY_RESET); - exynos_elb_writel(exynos, 1, PCIE_APP_INIT_RESET); - exynos_elb_writel(exynos, 0, PCIE_APP_INIT_RESET); + exynos_elb_writel(exynos, PCIE_CORE_RESET, val); + exynos_elb_writel(exynos, PCIE_STICKY_RESET, 1); + exynos_elb_writel(exynos, PCIE_NONSTICKY_RESET, 1); + exynos_elb_writel(exynos, PCIE_APP_INIT_RESET, 1); + exynos_elb_writel(exynos, PCIE_APP_INIT_RESET, 0); exynos_blk_writel(exynos, 1, PCIE_PHY_MAC_RESET); } @@ -198,7 +198,7 @@ static void exynos_pcie_assert_phy_reset(struct exynos_pcie *exynos) static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *exynos) { exynos_blk_writel(exynos, 0, PCIE_PHY_GLOBAL_RESET); - exynos_elb_writel(exynos, 1, PCIE_PWR_RESET); + exynos_elb_writel(exynos, PCIE_PWR_RESET, 1); exynos_blk_writel(exynos, 0, PCIE_PHY_COMMON_RESET); exynos_blk_writel(exynos, 0, PCIE_PHY_CMN_REG); exynos_blk_writel(exynos, 0, PCIE_PHY_TRSVREG_RESET); @@ -328,8 +328,8 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos) exynos_pcie_assert_reset(exynos); /* assert LTSSM enable */ - exynos_elb_writel(exynos, PCIE_ELBI_LTSSM_ENABLE, - PCIE_APP_LTSSM_ENABLE); + exynos_elb_writel(exynos, PCIE_APP_LTSSM_ENABLE, + PCIE_ELBI_LTSSM_ENABLE); /* check if the link is up or not */ if (!dw_pcie_wait_for_link(pp)) @@ -348,7 +348,7 @@ static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *exynos) u32 val; val = exynos_elb_readl(exynos, PCIE_IRQ_PULSE); - exynos_elb_writel(exynos, val, PCIE_IRQ_PULSE); + exynos_elb_writel(exynos, PCIE_IRQ_PULSE, val); } static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *exynos) @@ -358,7 +358,7 @@ static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *exynos) /* enable INTX interrupt */ val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; - exynos_elb_writel(exynos, val, PCIE_IRQ_EN_PULSE); + exynos_elb_writel(exynos, PCIE_IRQ_EN_PULSE, val); } static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) @@ -387,7 +387,7 @@ static void exynos_pcie_msi_init(struct exynos_pcie *exynos) /* enable MSI interrupt */ val = exynos_elb_readl(exynos, PCIE_IRQ_EN_LEVEL); val |= IRQ_MSI_ENABLE; - exynos_elb_writel(exynos, val, PCIE_IRQ_EN_LEVEL); + exynos_elb_writel(exynos, PCIE_IRQ_EN_LEVEL, val); } static void exynos_pcie_enable_interrupts(struct exynos_pcie *exynos)