From patchwork Fri Nov 25 10:57:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 9447349 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0E3C460778 for ; Fri, 25 Nov 2016 10:57:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 10DD827D13 for ; Fri, 25 Nov 2016 10:57:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 05D962807E; Fri, 25 Nov 2016 10:57:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 202DF27FB6 for ; Fri, 25 Nov 2016 10:57:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753083AbcKYK5o (ORCPT ); Fri, 25 Nov 2016 05:57:44 -0500 Received: from mail-pf0-f193.google.com ([209.85.192.193]:32907 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752940AbcKYK5n (ORCPT ); Fri, 25 Nov 2016 05:57:43 -0500 Received: by mail-pf0-f193.google.com with SMTP id 144so2924707pfv.0; Fri, 25 Nov 2016 02:57:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EPFFsreXj5SJRsxVQrgE4tupuqOg7cBUJPR2syJelSk=; b=xO0mAvmlzPOfeWxZjSINLuwpAzulPAHlb49WhTKKkaxF9SQ21NzbazAhxAgSEZMEZw UWTpFguUoPlMZXucJbmZyHb3MKcsdpnKWAlF+Zcv5/kvwFcPX1uKbC6YF5HQM6q61M70 S/GP7Czu0ExeJFOgXD9iIpRnM75oHq62eHklIKIiTSIDlRX7tf/MJnhgkyIrgn6RrmJw OzkAdDJnyaLG3bThCdwsANEhxs8P1PhS1RvOnCwNLFF96WHDIzydeMtYF+U5eEy8aPEo Xc3DSg0uz8Yf5CF6zvLTykp1LL8tEV1XVKo+m9dPoSfZlSeklZhvyQZFUHaAicltrubo z6Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EPFFsreXj5SJRsxVQrgE4tupuqOg7cBUJPR2syJelSk=; b=Dnv/jO/2dBHoNibqKv/afwWwAoMl+0P5d0TRlS1HYRo6WixnyHd5kUQGZej/V7he9E IOmWKX6dSjrhyVSHWFxTLSmSIT/xdvIN32pRGj+mZPy+amxPpA3Fbo+iME7SWfgO4znJ iOq0c0V8WWM7SL586LTvQMBl/HYhrBVtMXWnmQNgoK7mkJwTrRXzoaC0e21gOXa98FaT gamAqsrakEnVjPTNBqOoCKPXzLIRaRsTsWM9fVNVzFS/cuGFOtiGSeIw87nPxUxM2fH6 07lZgYlyJyFzkxyjhueMv6jIrZb3Yms23IxfW6souztkZtARilP97Pxj8bJGBfIobdFZ xn1Q== X-Gm-Message-State: AKaTC03bMeTSKN5r+Gd/CYUC9anqmKKsCFatJPJvq8vIi+Fn5XxGrc/as4QcVfCvDFMGkg== X-Received: by 10.84.217.216 with SMTP id d24mr16203282plj.10.1480071462488; Fri, 25 Nov 2016 02:57:42 -0800 (PST) Received: from localhost (port-2820.pppoe.wtnet.de. [84.46.11.15]) by smtp.gmail.com with ESMTPSA id l7sm66961298pfg.35.2016.11.25.02.57.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Nov 2016 02:57:42 -0800 (PST) From: Thierry Reding To: Bjorn Helgaas Cc: Arnd Bergmann , Tomasz Nowicki , Liviu Dudau , Lorenzo Pieralisi , Vidya Sagar , linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v4 06/10] PCI: tegra: Implement PCA enable workaround Date: Fri, 25 Nov 2016 11:57:14 +0100 Message-Id: <20161125105718.3866-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161125105718.3866-1-thierry.reding@gmail.com> References: <20161125105718.3866-1-thierry.reding@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding Tegra210's PCIe controller has a bug that requires the PCA (performance counter) feature to be enabled. If this isn't done, accesses to device configuration space will hang the chip for tens of seconds. Implement the workaround. Based on commit 514e19138af2 ("pci: tegra: implement PCA enable workaround") from U-Boot by Stephen Warren . Signed-off-by: Thierry Reding --- drivers/pci/host/pci-tegra.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index d5206fa53353..4bfaac6d3582 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -188,6 +188,9 @@ #define RP_VEND_XP 0x00000f00 #define RP_VEND_XP_DL_UP (1 << 30) +#define RP_VEND_CTL2 0x00000fa8 +#define RP_VEND_CTL2_PCA_ENABLE (1 << 7) + #define RP_PRIV_MISC 0x00000fe0 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0) #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0) @@ -252,6 +255,7 @@ struct tegra_pcie_soc { bool has_intr_prsnt_sense; bool has_cml_clk; bool has_gen2; + bool force_pca_enable; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -556,6 +560,12 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port) afi_writel(port->pcie, value, ctrl); tegra_pcie_port_reset(port); + + if (soc->force_pca_enable) { + value = readl(port->base + RP_VEND_CTL2); + value |= RP_VEND_CTL2_PCA_ENABLE; + writel(value, port->base + RP_VEND_CTL2); + } } static void tegra_pcie_port_disable(struct tegra_pcie_port *port) @@ -2046,6 +2056,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .has_intr_prsnt_sense = false, .has_cml_clk = false, .has_gen2 = false, + .force_pca_enable = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2060,6 +2071,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .has_intr_prsnt_sense = true, .has_cml_clk = true, .has_gen2 = false, + .force_pca_enable = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2073,6 +2085,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .has_intr_prsnt_sense = true, .has_cml_clk = true, .has_gen2 = true, + .force_pca_enable = false, }; static const struct of_device_id tegra_pcie_of_match[] = {