From patchwork Wed Jan 4 12:34:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaehoon Chung X-Patchwork-Id: 9496605 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9C11360413 for ; Wed, 4 Jan 2017 12:37:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8B3DE2787C for ; Wed, 4 Jan 2017 12:37:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7EEF227F17; Wed, 4 Jan 2017 12:37:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5CFEC27E5A for ; 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Wed, 4 Jan 2017 21:34:36 +0900 (KST) Received: from epcpsbgm1new.samsung.com (u26.gpu120.samsung.co.kr [203.254.230.26]) by epcas1p1.samsung.com (KnoxPortal) with ESMTP id 20170104123436epcas1p1651443c5fe13f67006864aed2f70fa9d~WkaekEAEw0688506885epcas1p1D; Wed, 4 Jan 2017 12:34:36 +0000 (GMT) X-AuditID: b6c32a39-f79256d000001a75-fc-586cebdcd7f6 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id DC.F8.28252.CDBEC685; Wed, 4 Jan 2017 21:34:36 +0900 (KST) Received: from localhost.localdomain ([10.113.62.216]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OJ900IEZ9LNGDB0@mmp2.samsung.com>; Wed, 04 Jan 2017 21:34:36 +0900 (KST) From: Jaehoon Chung To: linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, kgene@kernel.org, krzk@kernel.org, kishon@ti.com, jingoohan1@gmail.com, vivek.gautam@codeaurora.org, pankaj.dubey@samsung.com, alim.akhtar@samsung.com, cpgs@samsung.com, Jaehoon Chung Subject: [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework Date: Wed, 04 Jan 2017 21:34:34 +0900 Message-id: <20170104123435.30740-5-jh80.chung@samsung.com> X-Mailer: git-send-email 2.10.2 In-reply-to: <20170104123435.30740-1-jh80.chung@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAAzVSWUwTURTlzdDpQCyOFcsLisIYNYDUTmnhoeASjZlEVBJ/Go3BESYtoQt2 WhRjImqoiiwicUENmxANokCjUtxFpIaoo+FDg4q4RZSgIrgSiaVT/86995x7Tm4uiSvHZZFk jtXB262cmSZCg6/cjdUkvBgyGzQXR+PRQPUVAjXsNaGPnbGopuuRDD3745Khc2NVclT+dghH j9+XEEgUW+Wo9+ppAj2s9hLohHgTQ41Pn2Co/vKYHBXd6JKj+789+HKKba5uBmxvWSnGdpx8 KWdr3U7W3XSQYMsuNQHW+6wdY0fdszPIjXyqieeyeXs0b82yZedYjWn0mg2ZKzP1SRomgUlB yXS0lbPwafSq9IyE1TlmX346Op8zO32tDE4Q6EVLU+02p4OPNtkERxq9iWG0akaTrNZqtWpd 4ubFWr2PsoU39VUNY3m35u4oGq0BhWA8qhiEkJDSwXf3GoCEVfBxfwtRDEJJJeUBUGwuDBT7 MThy5JSPRfoVo9dUUv80gHdKb2BS8QvA/o5yYnIVQS2E7T+82CQOp6LgSO91/yac+oPB2ze/ +gfTqXTo+jsgm8TB1Dz44l2FP4eCWgJdZx8QUqY5sE7s8vNDqFQ40djqd4NUjxweOPE6WIoU Bd23cYm/CraInoB2OvzkvSSX8EzYNNEX0B4CcGKsjZCKEgD7Lp/HJFYifDXQ79+EU2Hw8/cS mWSggAdcSonCwsrDHQGDFbC4dzBwo3IAv9W04ofBrFoQ1ARUfJ5gMfICk6dXC5xFcFqN6iyb xQ38jxeX4gHdj9I7AUUCeoriXH2uQSnj8oUCSyeAJE6HK34Mmg1KRTZXsJO32zLtTjMvdAK9 71AVeOSMLJvvja2OTEaXxOi0OoZJ1mq0dITizJ4lBiVl5Bx8Ls/n8fb/OowMiSwEEWsWbawb a4iJ3z3V+PzqWXHGttLh2nUleuJNODdkTqpvSYzZ91KVWB56POVn4/wvIV+//zzWRoTNb9ZV KhvEDZXetME47q1q95v1deqItYt7drVtLZuZO171oWgkbEdB0IWIgilloDvuiWvBw9rSo3fD t+U8nfdFbIyP2X7o/NC0ZaF0sGDimDjcLnD/AJOShb+OAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCIsWRmVeSWpSXmKPExsVy+t9jQd07r3MiDM6+lLR4MG8bm8WSpgyL l4c0LeYfOcdqceNXG6vFii8z2S36H79mtrjwtIfN4vz5DewWl3fNYbM4O+84m8WM8/uYLJZe v8hksWjrF3aL1r1H2C1O/NzB7CDgsWbeGkaPy329TB47Z91l91iwqdRj06pONo++LasYPY7f 2M7k8XmTXABHlJtNRmpiSmqRQmpecn5KZl66rVJoiJuuhZJCXmJuqq1ShK5vSJCSQlliTimQ Z2SABhycA9yDlfTtEtwybs18y1SwX7mi9fN8xgbG37JdjBwcEgImEp93i3UxcgKZYhIX7q1n 62Lk4hASmMUo8WD3K0aQhJDAD0aJji9+IDabgI7E9m/HmUBsEQFZiY+X97CB2MwCv5gklu4z BbGFBXwk2v4+YAWxWQRUJe48mQg2h1fAWqJt+Rk2iGXyEgvPHwGbwylgI/Fv6QYmiF3WEn0n JzBNYORdwMiwilEitSC5oDgpPdcwL7Vcrzgxt7g0L10vOT93EyM4hp5J7WA8uMv9EKMAB6MS D6/A/ZwIIdbEsuLK3EOMEhzMSiK8314AhXhTEiurUovy44tKc1KLDzGaAh02kVlKNDkfGN95 JfGGJuYm5sYGFuaWliZGSuK8jbOfhQsJpCeWpGanphakFsH0MXFwSjUwbr+1Q/JnRKzhyjmJ iwv/LpVZuoCH11fnkWLy0e0HGE3abivpxK7aszHVqrzCcqP4s2krdZ/GFlpPX7lBkH/xG9HF VS0mFlET7rwzCL5zQPf6jusc+yf/af94XeC9sNbB7lcTBKZLNqsf2qorVfFi3w7Vc0eW2N2/ KN0b6Xg5+2LdMefQ46oNnEosxRmJhlrMRcWJAE+pg7G3AgAA X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170104123436epcas1p1651443c5fe13f67006864aed2f70fa9d X-Msg-Generator: CA X-Sender-IP: 203.254.230.26 X-Local-Sender: =?UTF-8?B?7KCV7J6s7ZuIG1RpemVuIFBsYXRmb3JtIExhYihTL1fshLw=?= =?UTF-8?B?7YSwKRvsgrzshLHsoITsnpAbUzUo7LGF7J6EKS/ssYXsnoQ=?= X-Global-Sender: =?UTF-8?B?SmFlaG9vbiBDaHVuZxtUaXplbiBQbGF0Zm9ybSBMYWIuG1Nh?= =?UTF-8?B?bXN1bmcgRWxlY3Ryb25pY3MbUzUvU2VuaW9yIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG1NUQUYbQzEwVjgxMTE=?= CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-HopCount: 7 X-CMS-RootMailID: 20170104123436epcas1p1651443c5fe13f67006864aed2f70fa9d X-RootMTR: 20170104123436epcas1p1651443c5fe13f67006864aed2f70fa9d References: <20170104123435.30740-1-jh80.chung@samsung.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch is for using PHY generic framework. To maintain backward compatibility, check whether phy is supported or not with 'using_phy'. And if someone use the old dt-file, display the "deprecated" message. But it's still working fine with it. Signed-off-by: Jaehoon Chung Acked-by: Krzysztof Kozlowski Acked-by: Jingoo Han Reviewed-by: Pankaj Dubey Reviewed-by: Alim Akhtar --- Changelog on V2: - This patch is split from previous PATCH[1/4] - Maintain the backward compatibility - Adds 'using_phy' for cheching whether phy framework is used or not - Adds 'DEPRECATED' message for old dt-binding way drivers/pci/host/pci-exynos.c | 61 +++++++++++++++++++++++++++++++++++-------- 1 file changed, 50 insertions(+), 11 deletions(-) diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index feed0fd..34f2eed 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -110,6 +111,10 @@ struct exynos_pcie { struct exynos_pcie_clk_res *clk_res; const struct exynos_pcie_ops *ops; int reset_gpio; + + /* For Generic PHY Framework */ + bool using_phy; + struct phy *phy; }; struct exynos_pcie_ops { @@ -135,6 +140,10 @@ static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev, if (IS_ERR(ep->mem_res->elbi_base)) return PTR_ERR(ep->mem_res->elbi_base); + /* If using the PHY framework, doesn't need to get other resource */ + if (ep->using_phy) + return 0; + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ep->mem_res->phy_base = devm_ioremap_resource(dev, res); if (IS_ERR(ep->mem_res->phy_base)) @@ -396,17 +405,28 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie) } exynos_pcie_assert_core_reset(exynos_pcie); - exynos_pcie_assert_phy_reset(exynos_pcie); - exynos_pcie_deassert_phy_reset(exynos_pcie); - exynos_pcie_power_on_phy(exynos_pcie); - exynos_pcie_init_phy(exynos_pcie); - - /* pulse for common reset */ - exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1, - PCIE_PHY_COMMON_RESET); - udelay(500); - exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0, - PCIE_PHY_COMMON_RESET); + + if (exynos_pcie->using_phy) { + phy_reset(exynos_pcie->phy); + + exynos_pcie_writel(exynos_pcie->mem_res->elbi_base, 1, + PCIE_PWR_RESET); + + phy_power_on(exynos_pcie->phy); + phy_init(exynos_pcie->phy); + } else { + exynos_pcie_assert_phy_reset(exynos_pcie); + exynos_pcie_deassert_phy_reset(exynos_pcie); + exynos_pcie_power_on_phy(exynos_pcie); + exynos_pcie_init_phy(exynos_pcie); + + /* pulse for common reset */ + exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1, + PCIE_PHY_COMMON_RESET); + udelay(500); + exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0, + PCIE_PHY_COMMON_RESET); + } exynos_pcie_deassert_core_reset(exynos_pcie); dw_pcie_setup_rc(pp); @@ -420,6 +440,11 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie) if (!dw_pcie_wait_for_link(pp)) return 0; + if (exynos_pcie->using_phy) { + phy_power_off(exynos_pcie->phy); + return -ETIMEDOUT; + } + while (exynos_pcie_readl(exynos_pcie->mem_res->phy_base, PCIE_PHY_PLL_LOCKED) == 0) { val = exynos_pcie_readl(exynos_pcie->mem_res->block_base, @@ -633,6 +658,17 @@ static int __init exynos_pcie_probe(struct platform_device *pdev) exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); + /* Assume that controller doesn't use the PHY framework */ + exynos_pcie->using_phy = false; + + exynos_pcie->phy = devm_of_phy_get(dev, np, NULL); + if (IS_ERR(exynos_pcie->phy)) { + if (PTR_ERR(exynos_pcie->phy) == -EPROBE_DEFER) + return PTR_ERR(exynos_pcie->phy); + dev_warn(dev, "Use the 'phy' property. Current DT of pci-exynos was deprecated!!\n"); + } else + exynos_pcie->using_phy = true; + if (exynos_pcie->ops && exynos_pcie->ops->get_mem_resources) { ret = exynos_pcie->ops->get_mem_resources(pdev, exynos_pcie); if (ret) @@ -657,6 +693,9 @@ static int __init exynos_pcie_probe(struct platform_device *pdev) return 0; fail_probe: + if (exynos_pcie->using_phy) + phy_exit(exynos_pcie->phy); + if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources) exynos_pcie->ops->deinit_clk_resources(exynos_pcie); return ret;