From patchwork Thu Jan 12 02:17:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaehoon Chung X-Patchwork-Id: 9511769 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8E18160710 for ; Thu, 12 Jan 2017 02:17:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 811B128697 for ; Thu, 12 Jan 2017 02:17:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7453F286A7; Thu, 12 Jan 2017 02:17:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 97A3C28697 for ; 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Thu, 12 Jan 2017 11:17:22 +0900 (KST) Received: from epcpsbgm1new.samsung.com (u26.gpu120.samsung.co.kr [203.254.230.26]) by epcas1p3.samsung.com (KnoxPortal) with ESMTP id 20170112021722epcas1p308bc0e69d541fe0e46445c2a464857b2~Y5J2EaNxD0083100831epcas1p3O; Thu, 12 Jan 2017 02:17:22 +0000 (GMT) X-AuditID: b6c32a35-f79956d000002021-d0-5876e7329fd3 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id FD.15.08931.237E6785; Thu, 12 Jan 2017 11:17:22 +0900 (KST) Received: from localhost.localdomain ([10.113.62.216]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OJN00EIWACXY0B0@mmp1.samsung.com>; Thu, 12 Jan 2017 11:17:22 +0900 (KST) From: Jaehoon Chung To: linux-pci@vger.kernel.org Cc: helgaas@google.com, krzk@kernel.org, linux-kernel@vger.kernel.org, jingoohan1@gmail.com, javier@osg.samsung.com, kgene@kernel.org, linux-samsung-soc@vger.kernel.org, cpgs@samsung.com, Jaehoon Chung Subject: [PATCH V2 3/4] PCI: exynos: Use the bitops API to operate the bit shifting Date: Thu, 12 Jan 2017 11:17:18 +0900 Message-id: <20170112021719.24986-3-jh80.chung@samsung.com> X-Mailer: git-send-email 2.10.2 In-reply-to: <20170112021719.24986-1-jh80.chung@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCKsWRmVeSWpSXmKPExsWy7bCmga7R87IIgx9nlSxeHtK0mPV8D6vF m7drmCxu/GpjtVjxZSa7Rf/j18wW589vYLe4vGsOm8XZecfZLGac38fkwOWxc9Zddo8Fm0o9 Nq3qZPPY0g/k9W1ZxejxeZNcAFtUqk1GamJKapFCal5yfkpmXrqtkndwvHO8qZmBoa6hpYW5 kkJeYm6qrZKLT4CuW2YO0GFKCmWJOaVAoYDE4mIlfTubovzSklSFjPziElulaENDIz1DA3M9 IyMjPRPjWCsjU6CShNSMzz29LAWdEhU/Lt5iamCcItLFyMkhIWAiMenFbCYIW0ziwr31bF2M XBxCAjsYJd5cOsEO4bQzSVz/eY4NpmP59g5miMRyRokF2z6wQDg/GCXmHP/MAlLFJqAjsf3b cbC5IgKyEh8v7wGbyyzwglGi8eRlsCJhgVCJE9NPsoPYLAKqEt9XPgGL8wpYS5yf0cQMsU5e YuH5I2CDOAVsJNat2Qq2TUKgnV1iy4Q21i5GDiBHVmLTAah6F4mm9R1QDwlLvDq+hR3ClpZY 9e8WE0RvN6PEvy8b2SCcHkaJW1tXQ3UYS9x/cA9sErMAn8S7rz1QC3glOtqEIEwPiQ8HEiCq HSUerZwPDYp+Romes/uZJzDKLGBkWMUollpQnJueWmxYYKhXnJhbXJqXrpecn7uJEZyitEx3 ME4553OIUYCDUYmHV8C+LEKINbGsuDL3EKMEB7OSCK/uE6AQb0piZVVqUX58UWlOavEhRlNg OE1klhJNzgemz7ySeEMTM0MTIxNDQ3MjAyMlcd7FjdYRQgLpiSWp2ampBalFMH1MHJxSDYym GzKY91jUd9pd5OqTfjT7Q/hWxYATTUsOJV1tumSxldPjEnP3BJej2q3fJ/SeWi70fvURzlWn f28RXOu8hO10nP78TV+ymjfNKFvi122nuupa4vnPrv7av5XehU9qvf3ksb9g1Jm/FbO+MN89 ME+kfP9Bh2l8f67/PPOzIlNu0qdNt812vT+yRImlOCPRUIu5qDgRAOct7SdnAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrHLMWRmVeSWpSXmKPExsVy+t9jAV2j52URBl93iVm8PKRpMev5HlaL N2/XMFnc+NXGarHiy0x2i/7Hr5ktzp/fwG5xedccNouz846zWcw4v4/Jgctj56y77B4LNpV6 bFrVyeaxpR/I69uyitHj8ya5ALYoN5uM1MSU1CKF1Lzk/JTMvHRbpdAQN10LJYW8xNxUW6UI Xd+QICWFssScUiDPyAANODgHuAcr6dsluGV87ullKeiUqPhx8RZTA+MUkS5GTg4JAROJ5ds7 mCFsMYkL99azdTFycQgJLGWU+PZvLRtIQkjgB6PE7HkxIDabgI7E9m/HmUBsEQFZiY+X94DV MAu8YJT4vEwSxBYWCJU4Mf0kO4jNIqAq8X3lExYQm1fAWuL8jCaoZfISC88fAZvDKWAjsW7N VhaIXdYSJxedZZ3AyLuAkWEVo0RqQXJBcVJ6rmFearlecWJucWleul5yfu4mRnDYP5PawXhw l/shRgEORiUe3gzHsggh1sSy4srcQ4wSHMxKIry6T4BCvCmJlVWpRfnxRaU5qcWHGE2BDpvI LCWanA+MybySeEMTcxNzYwMLc0tLEyMlcd7G2c/ChQTSE0tSs1NTC1KLYPqYODilGhhdRFct +mE+T//64kJ5a2lTDt9k6WO3u3LPpfRoz16kMz325sWyyPxDLqob2DY+cLdXrlKbbd/KdkZL XuStbbPiNLPc2Q4l4s43MhLnX/5jvyuUdbF6bInyY4ntUpd39Em1TDdl2yn1Uv5y+661N6Ys WbO6MPGtZqHBFkYmeZ0cB82kM8rV4kosxRmJhlrMRcWJAC/iqCSRAgAA X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170112021722epcas1p308bc0e69d541fe0e46445c2a464857b2 X-Msg-Generator: CA X-Sender-IP: 203.254.230.26 X-Local-Sender: =?UTF-8?B?7KCV7J6s7ZuIG1RpemVuIFBsYXRmb3JtIExhYihTL1fshLw=?= =?UTF-8?B?7YSwKRvsgrzshLHsoITsnpAbUzUo7LGF7J6EKS/ssYXsnoQ=?= X-Global-Sender: =?UTF-8?B?SmFlaG9vbiBDaHVuZxtUaXplbiBQbGF0Zm9ybSBMYWIuG1Nh?= =?UTF-8?B?bXN1bmcgRWxlY3Ryb25pY3MbUzUvU2VuaW9yIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG1NUQUYbQzEwVjgxMTE=?= CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-HopCount: 7 X-CMS-RootMailID: 20170112021722epcas1p308bc0e69d541fe0e46445c2a464857b2 X-RootMTR: 20170112021722epcas1p308bc0e69d541fe0e46445c2a464857b2 References: <20170112021719.24986-1-jh80.chung@samsung.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Just use the bitops api to operate the bit. Signed-off-by: Jaehoon Chung Reviewed-by: Pankaj Dubey Acked-by: Krzysztof Kozlowski --- Changelog on V2: - None drivers/pci/host/pci-exynos.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index 3a7e09b..6cbc1cc 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -40,19 +40,19 @@ struct exynos_pcie { /* PCIe ELBI registers */ #define PCIE_IRQ_PULSE 0x000 -#define IRQ_INTA_ASSERT (0x1 << 0) -#define IRQ_INTB_ASSERT (0x1 << 2) -#define IRQ_INTC_ASSERT (0x1 << 4) -#define IRQ_INTD_ASSERT (0x1 << 6) +#define IRQ_INTA_ASSERT BIT(0) +#define IRQ_INTB_ASSERT BIT(2) +#define IRQ_INTC_ASSERT BIT(4) +#define IRQ_INTD_ASSERT BIT(6) #define PCIE_IRQ_LEVEL 0x004 #define PCIE_IRQ_SPECIAL 0x008 #define PCIE_IRQ_EN_PULSE 0x00c #define PCIE_IRQ_EN_LEVEL 0x010 -#define IRQ_MSI_ENABLE (0x1 << 2) +#define IRQ_MSI_ENABLE BIT(2) #define PCIE_IRQ_EN_SPECIAL 0x014 #define PCIE_PWR_RESET 0x018 #define PCIE_CORE_RESET 0x01c -#define PCIE_CORE_RESET_ENABLE (0x1 << 0) +#define PCIE_CORE_RESET_ENABLE BIT(0) #define PCIE_STICKY_RESET 0x020 #define PCIE_NONSTICKY_RESET 0x024 #define PCIE_APP_INIT_RESET 0x028 @@ -61,7 +61,7 @@ struct exynos_pcie { #define PCIE_ELBI_LTSSM_ENABLE 0x1 #define PCIE_ELBI_SLV_AWMISC 0x11c #define PCIE_ELBI_SLV_ARMISC 0x120 -#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21) +#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21) /* PCIe Purple registers */ #define PCIE_PHY_GLOBAL_RESET 0x000 @@ -79,27 +79,27 @@ struct exynos_pcie { #define PCIE_PHY_DCC_FEEDBACK 0x014 #define PCIE_PHY_PLL_DIV_1 0x05c #define PCIE_PHY_COMMON_POWER 0x064 -#define PCIE_PHY_COMMON_PD_CMN (0x1 << 3) +#define PCIE_PHY_COMMON_PD_CMN BIT(3) #define PCIE_PHY_TRSV0_EMP_LVL 0x084 #define PCIE_PHY_TRSV0_DRV_LVL 0x088 #define PCIE_PHY_TRSV0_RXCDR 0x0ac #define PCIE_PHY_TRSV0_POWER 0x0c4 -#define PCIE_PHY_TRSV0_PD_TSV (0x1 << 7) +#define PCIE_PHY_TRSV0_PD_TSV BIT(7) #define PCIE_PHY_TRSV0_LVCC 0x0dc #define PCIE_PHY_TRSV1_EMP_LVL 0x144 #define PCIE_PHY_TRSV1_RXCDR 0x16c #define PCIE_PHY_TRSV1_POWER 0x184 -#define PCIE_PHY_TRSV1_PD_TSV (0x1 << 7) +#define PCIE_PHY_TRSV1_PD_TSV BIT(7) #define PCIE_PHY_TRSV1_LVCC 0x19c #define PCIE_PHY_TRSV2_EMP_LVL 0x204 #define PCIE_PHY_TRSV2_RXCDR 0x22c #define PCIE_PHY_TRSV2_POWER 0x244 -#define PCIE_PHY_TRSV2_PD_TSV (0x1 << 7) +#define PCIE_PHY_TRSV2_PD_TSV BIT(7) #define PCIE_PHY_TRSV2_LVCC 0x25c #define PCIE_PHY_TRSV3_EMP_LVL 0x2c4 #define PCIE_PHY_TRSV3_RXCDR 0x2ec #define PCIE_PHY_TRSV3_POWER 0x304 -#define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7) +#define PCIE_PHY_TRSV3_PD_TSV BIT(7) #define PCIE_PHY_TRSV3_LVCC 0x31c static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)