From patchwork Sat Jan 28 20:48:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 9543461 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 48B8F60415 for ; Sat, 28 Jan 2017 20:49:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3AC9928338 for ; Sat, 28 Jan 2017 20:49:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2F6AB281C3; Sat, 28 Jan 2017 20:49:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0ADA928338 for ; Sat, 28 Jan 2017 20:49:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751960AbdA1Uth (ORCPT ); Sat, 28 Jan 2017 15:49:37 -0500 Received: from mail-lf0-f43.google.com ([209.85.215.43]:35798 "EHLO mail-lf0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752007AbdA1Ute (ORCPT ); Sat, 28 Jan 2017 15:49:34 -0500 Received: by mail-lf0-f43.google.com with SMTP id n124so177285781lfd.2 for ; Sat, 28 Jan 2017 12:49:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3s6Avui8YGxvEPNCJNM30Yp0KX+IdxEsgyfbyVNScfU=; b=GizuVz+hPoO099zPjvDHy8I1AMsgBx/3icf1wbzo+HYAmn65aDorQJ+TqGJxNIGWcM pvgT19chTU0FiQYkprtOGteoPrUR2el4OcZiumzOnWYZ3CLyPnmgzmgWnQeQ+9zuEbYx wjkE8f/US7uOClouM5bX4fhI5IR6+scGubGA4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3s6Avui8YGxvEPNCJNM30Yp0KX+IdxEsgyfbyVNScfU=; b=ucA6AhSnDZ5jSSvvB9jFZQNXA0MMxdvEiOYkKlpMvk9ypkWLARKJj2ny3E8O6SpgT1 5claoo4gRLXlKm39252KWIX2l/FA9xdl0b2tZ9UGnfKmQwcCORM92Duxcmgc5Jo3fdvC J+AjpY43GvUsWYPk5WZX32fPqN0RJg2A6kGB+Z+tldj6GOBwNLEWUKwELiv+ZWXCurXt 5GTP1aozWUgaKpgEq+imPlYYJJRNC7souamq/SqdD7fDOxXc/w+RMKOJW3oT8hOIbz96 2eSb5vap0BEOlEFnN7jNXv79Z0N6o3fIoNyN48ypYKZYD0ZSwMFh4h4kCf6EYR0Hqlae 51Bw== X-Gm-Message-State: AIkVDXI5lWvA/2cpB0ilNjQ70ZYBoy0M2XxsgG/UarE5FhfDOF8foM9vPJCa4orJjq3tRKEl X-Received: by 10.46.6.17 with SMTP id 17mr5437505ljg.14.1485636548560; Sat, 28 Jan 2017 12:49:08 -0800 (PST) Received: from localhost.localdomain (c-357171d5.014-348-6c756e10.cust.bredbandsbolaget.se. [213.113.113.53]) by smtp.gmail.com with ESMTPSA id m18sm2314843lfe.45.2017.01.28.12.49.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 28 Jan 2017 12:49:07 -0800 (PST) From: Linus Walleij To: Hans Ulli Kroll , Florian Fainelli , Bjorn Helgaas Cc: Janos Laube , Paulius Zaleckas , openwrt-devel@openwrt.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Linus Walleij Subject: [PATCH 4/4] ARM: dts: add PCI to the Gemini DTSI Date: Sat, 28 Jan 2017 21:48:39 +0100 Message-Id: <20170128204839.18330-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170128204839.18330-1-linus.walleij@linaro.org> References: <20170128204839.18330-1-linus.walleij@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Cortina Gemini has an internal PCI root bus, add this to the device tree. Cc: Janos Laube Cc: Paulius Zaleckas Cc: Hans Ulli Kroll Cc: Florian Fainelli Signed-off-by: Linus Walleij --- PCI maintainers: this is FYI only, I will funnel this to the ARM SoC tree once we are done with the PCI driver. --- arch/arm/boot/dts/gemini.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index 405d6cedf409..df5630958038 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -99,4 +99,49 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pci@50000000 { + compatible = "cortina,gemini-pci"; + reg = <0x50000000 0x100>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, /* PCI A */ + <26 IRQ_TYPE_LEVEL_HIGH>, /* PCI B */ + <27 IRQ_TYPE_LEVEL_HIGH>, /* PCI C */ + <28 IRQ_TYPE_LEVEL_HIGH>; /* PCI D */ + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + bus-range = <0x00 0x00>; /* Only root bus */ + /* PCI ranges mappings */ + ranges = /* 1MiB I/O space 0x50000000-0x500fffff */ + <0x01000000 0 0 0x50000000 0 0x00100000>, + /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ + <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; + + interrupt-map-mask = <0xff00 0 0 7>; + /* + * The interrupt map is done by sub-device and per-slot. + */ + interrupt-map = <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ + <0x4900 0 0 2 &pci_intc 1>, + <0x4a00 0 0 3 &pci_intc 2>, + <0x4b00 0 0 4 &pci_intc 3>, + <0x5000 0 0 1 &pci_intc 0>, /* Slot 10 */ + <0x5100 0 0 2 &pci_intc 1>, + <0x5200 0 0 3 &pci_intc 2>, + <0x5300 0 0 4 &pci_intc 3>, + <0x5800 0 0 1 &pci_intc 0>, /* Slot 11 */ + <0x5900 0 0 2 &pci_intc 1>, + <0x5a00 0 0 3 &pci_intc 2>, + <0x5b00 0 0 4 &pci_intc 3>, + <0x6000 0 0 1 &pci_intc 0>, /* Slot 12 */ + <0x6100 0 0 2 &pci_intc 1>, + <0x6200 0 0 3 &pci_intc 2>, + <0x6300 0 0 4 &pci_intc 3>; + pci_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; };